Stable operation of two-dimensional field-effect transistors with van der Waals integrated SrTiO₃ top-gate dielectrics

Abstract

The ultra-thin atomic layer structure of two-dimensional (2D) materials confers potential capabilities that extend and transcend Moore's law, while rendering them highly susceptible to environmental factors such as temperature fluctuations, adsorbates, and trap charges in adjacent dielectric materials. Consequently, the stability of 2D material-based devices has become critically important for the fabrication of low-power field-effect transistors (FETs). In this work, we constructed top-gated 2D FETs using monolayer MoS₂ and SrTiO₃ (STO) as the channel and dielectrics, respectively. We systematically investigated their temperature stability, electrical hysteresis and long-term stability under ambient conditions. Experimental results demonstrate that STO top-gated MoS₂ FETs exhibit remarkable stability, maintaining performance after one month of ambient exposure and showing no irreversible degradation under thermal (100 °C) and electrical stress conditions. This study provides valuable reference for enhancing the stability of low dimensional devices and for developing 2D devices with complex functionalities.

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Allen Jian Yang

Allen Jian Yang is a Professor at Academy for Advanced Interdisciplinary Science and Technology, University of Science and Technology Beijing (USTB). He received his BS degree from Fudan University in 2012 and PhD degree from Nanyang Technological University in 2017. Then he worked as a Research Fellow and a Senior Research Fellow at Nanyang Technological University before joining USTB in 2025. His current research focuses on micro- and nano-electronic devices based on two-dimensional semiconductors which are considered as some of the most promising material candidates in the post-Moore era.

Introduction

2D materials, with their unique ultra-thin layered structure and dangling bond-free surfaces, are advantageous for suppressing short-channel effects and achieving high carrier mobility, positioning them as some of the most promising materials to transcend Moore's law.^1–4 Low-power field-effect transistors (FETs) based on 2D materials hold tremendous potential in extending the battery life of mobile devices, reducing energy consumption to decrease carbon emissions, and minimizing dependence on electrical infrastructure to provide digital services to broader populations,^5,6,7 However, traditional dielectric material silicon oxide, due to its low dielectric constant and high leakage current caused by quantum tunneling effects in thin layers, cannot meet the requirements for dielectric materials in low-power FETs. In recent years, the semiconductor industry has been searching for high-κ dielectrics that are compatible with 2D materials, such as Al₂O₃^8,9 (κ ∼ 9), HfO₂¹⁰ (κ ∼ 25), TiO₂^11,12 (κ ∼ 40), etc. However, due to their inert interfaces that hinder bonding with two-dimensional materials, resulting in lower interface quality and high-density defects, their large-area high-quality integration with two-dimensional materials still poses significant challenges. Recently, some non-polar molecular crystals such as Sb₂O₃¹³ (κ ∼ 12) and CaF₂¹⁴ (κ ∼ 8) have also attracted interest and enabled the fabrication of high-quality back-gated devices. However, their integration as top gates with two-dimensional materials has not yet been demonstrated, even though such top-gate configurations are more suitable for very large-scale integration applications. Hexagonal boron nitride (h-BN) as a van der Waals insulator can form high-quality clean interfaces with two-dimensional materials,¹⁵ but due to the low dielectric constant (∼4), its use in low-power circuits is limited.

Recently, perovskite oxides, a large class of complex oxides bearing a series of exotic electrical, optical, and magnetic properties, have attracted significant attention.^16,17 Some 2D perovskite oxides, such as SrTiO₃ (STO), are considered highly promising gate dielectric materials for ultra-low-power field-effect transistors due to their exceptionally large dielectric constant, low interface trap density and high breakdown strength.^18–21 Consequently, the integration of perovskite oxide with 2D materials for fabricating ultra-low-power high-performance FETs has garnered substantial attention.^22–25 Growth of STO on 2D materials is severely hindered by the incompatibility in the lattice structure and growth conditions. Yang et al.¹⁹ and Huang et al.¹⁸ successfully combined exfoliated STO and MoS₂ together via a water-soluble sacrificial layer. This van der Waals (vdW) integration technique resolves structural mismatch issues, resulting in high-quality, clean STO–MoS₂ interfaces and enabling the fabrication of high-performance FETs.

FET stability is equally crucial for power consumption control.^15,26–30 Increased leakage current, threshold voltage drift, subthreshold swing (SS) degradation, and mobility reduction all contribute to higher power consumption. Factors such as gas adsorption and interface charge trapping can compromise FET stability. Therefore, reliability and stability analysis of the STO top-gated 2D FETs is essential. Seyed et al.³¹ recently conducted systematic stability measurements on few-layer MoS₂ FETs with STO as the bottom dielectric, discovering minimal hysteresis during vacuum measurements. However, due to structural limitations, significant hysteresis and performance degradation occurred under ambient conditions.

In this study, we fabricated high-performance STO top-gated TMD FETs using STO as the top dielectric material and monolayer MoS₂ as the channel material. These devices exhibited a current on/off ratio (I_on/I_off) exceeding 10⁷ at ±1 V, an SS of approximately 80 mV dec⁻¹, and an ultra-low gate leakage current on the order of 10⁻⁵ A cm⁻². We measured and analyzed their temperature stability, long-term stability, and hysteresis behavior under ambient conditions, demonstrating excellent encapsulation function of STO for 2D semiconductors. These results also confirm the immense potential of STO top-gate FETs for practical applications in low-power circuits.

Results and discussion

To avoid interference between different processing methods, we fabricated three devices with identical structures, utilizing graphene electrodes, the typical high-κ perovskite oxide STO as the top gate, and monolayer MoS₂ as the channel material. We obtained graphene electrodes and monolayer MoS₂ through mechanical exfoliation and isolated STO using a sacrificial layer-assisted approach. These materials were subsequently stacked into vdW heterostructures via polymer-assisted transfer. Electrodes were patterned and metallized using electron beam lithography (EBL). Detailed procedures are given in the Methods section. Fig. 1a and b presents an optical micrograph and schematic illustration of a representative device, while Fig. 1c shows an atomic force microscopy (AFM) image of the STO used, revealing a thickness of approximately 40.6 nm (Fig. 1d).

Fig. 1 (a) Optical micrograph and (b) schematic of a typical MoS₂ EFT with STO top-gate (TG) dielectrics. The scale bar in (a) is 5 μm. Gr stands for graphene. S and D represent the source and drain, respectively. The blue dashed line in (a) represents the region of AFM measurement in (c). (c) AFM image of the STO of the device. The scale bar in (c) is 1 μm. (d) The height of the STO is about 40.6 nm.

To determine the dielectric strength of STO, we employed a dual-gate measurement approach.^19,32 Details of this dual-gate measurement method can be found in the SI. Fig. 2a illustrates the schematic of the measurement device, which uses 285 nm of silicon dioxide and STO as the bottom and top-gate dielectrics, respectively, for monolayer graphene. The graphene thickness was verified by Raman spectroscopy (Fig. 2b). The conductance of monolayer graphene can be modulated simultaneously by top and bottom gates, causing the top gate transfer characteristic curves to shift with varying bottom gate voltages, as shown in Fig. 3c. Assuming parallel-plate capacitor models for both gates, the position of the Dirac point in the top gate transfer characteristic curves varies inversely with the ratio of top gate to bottom gate capacitances as a function of V_BG. The fitted curve is displayed in Fig. 3d, with a slope of 0.02 substituted into the following formula:

where ε_STO and t_STO are the dielectric constant and thickness of STO, respectively, while ε_SiO2 and t_SiO2 are the dielectric constant and thickness of SiO₂, respectively. Thus, the dielectric constant of the STO used was determined to be 27.8.

Fig. 2 (a) Schematic of the dual gate monolayer graphene device. The TG dielectric is STO which is the same as the device shown in Fig. 1. And the back-gate (BG) dielectrics is 285 nm SiO₂. (b) Raman spectrum of graphene in (a). The height of the G peak and 2D peak confirms that it is monolayer graphene. (c) I_DS as a function of top-gate voltage (V_TG) with different back-gate voltages (V_BG). The V_BG ranges from −10 V to 50 V, and the step is 10 V. (d) The relationship between the top-gate Dirac voltages and the back-gate, with the teal line representing the fitting curve, which has a slope of −0.02. (e) Schematic of a metal–insulator–metal (MIM) structure with an STO intermediate layer. (f) Leakage current density against the applied voltage of the MIM structure. The horizontal dashed line represents the low power limit standard according to IRDS.

Fig. 3 Electrical performance of a typical STO top-gated MoS₂ FET: (a) output curves of the device, with the V_TG ranging from 0 to 0.7 V in steps of 0.1 V and the V_DS fixed at 0.05 V. The inset shows the output curves in the small V_DS range, where the good linear relationship proves the ohmic contact between MoS₂ and the Gr electrodes. (b) and (c) Transfer characteristics of the device at different V_DS values in linear and logarithmic scales, showing an I_on/I_off exceeding 10⁷ within the ±1 V range. (d) The SS of approximately 80 mV dec⁻¹ remains stable across more than three orders of magnitude. The dashed line represents the theoretical limit of SS at room temperature.

To further evaluate the performance of STO as a dielectric material, we fabricated STO metal–insulator–metal (MIM) devices as shown in Fig. 2e, with optical microscopy images shown in Fig. S4. We applied sweeping voltages from −2 V to +2 V to the top Au electrode, recording the leakage current of STO. The test was performed 20 times, and Fig. 2f shows the relationship between leakage current density and sweeping voltage. In the range of −2 V to +2 V (the typical gate voltage range of our STO gate FETs is ±1 V), the leakage current density J is less than 10⁻⁴ A cm⁻², which is far below the low power limit requirements of the International Roadmap for Devices and Systems (IRDS).³³ This demonstrates the great application potential of STO for low-power FETs.

We measured the electrical properties of our fabricated devices, with all measurements conducted under ambient conditions at room temperature unless otherwise specified. Fig. 3a presents the transport characteristics of a typical STO top-gated MoS₂ FET (D1), where the excellent linear relationship between I_DS and V_DS in low voltage ranges confirms the formation of good ohmic contacts between the graphene electrodes and monolayer MoS₂. Fig. 3b displays the transfer characteristics of D1, exhibiting typical n-type transistor behavior. Fig. 3c demonstrates the transfer characteristics and leakage current of D1 under small V_DS conditions (V_DS = 0.05 V). Within a V_GS range of ±1 V, the device achieved an I_on/I_off exceeding 10⁷, with negligible hysteresis between forward and reverse V_TG sweeps.

The gate leakage current consistently remained around 10⁻⁵ A cm⁻². As is shown in Fig. 3d, the SS was approximately 80 mV dec⁻¹. The carrier mobility was extracted using the equation μ = (L/(WC_iV_DS)) (dI_DS/dV_GS), where L, W and C_i are the channel length, the channel width and the area capacitance of STO. The area capacitance of STO can be obtained through ε₀ε_STO/t_STO. From this, the carrier mobility of D1 is 47.7 cm² V⁻¹ s⁻¹. Detailed information about other STO top-gated MoS₂ FETs can be found in Table S1.

The high dielectric constant, minimal hysteresis, high I_on/I_off, low SS, and high carrier mobility collectively validate the high quality of our devices and the clean channel–dielectric material interface.

We investigated device stability under elevated temperature conditions, with all heat treatments and measurements performed in an ambient environment. D1 was heated from 25 °C to 100 °C in 25 °C increments, with electrical measurements conducted after 30 minutes of stabilization at each temperature, followed by cooling back to 25 °C. The transfer characteristics at V_DS = 0.05 V are shown in Fig. 4a, while Fig. 4b illustrates the threshold voltage and carrier mobility variations at different temperatures. Fig. 4c presents the SS and leakage current behavior of D1. The dashed lines in Fig. 4a and c and the green point in Fig. 4b represent the condition after cooling back down. With increasing temperature, the MoS₂ transfer characteristics exhibited significant changes without catastrophic consequences: the threshold voltage shifted negatively along the V_GS axis, carrier mobility decreased to some extent, OFF-state current remained nearly constant, and ON-state current reduction did not exceed one order of magnitude. Throughout the heating process, the leakage current (I_GS) remained stable. At 100 °C, the hysteresis between forward and reverse sweeps noticeably increased (Fig. S5), yet the device still exhibits normal operation at ±1 V gate sweeping voltage. The relationship between carrier mobility in monolayer MoS₂ and temperature can typically be expressed as follows:³⁴

μ ∝ T^−γ, (2)

where T is the temperature of the device, while γ represents the temperature exponent. For the monolayer MoS₂ under ideal conditions, the temperature exponent near room temperature typically ranges between −1.7 and −2.^34–37 Our fitted value of approximately −2.35 suggests that besides the intrinsic carrier mobility decrease in MoS₂ due to phonon scattering effects with increasing temperature,³⁷ elevated temperatures enhanced charge capture and release processes at the STO–MoS₂ interface. S vacancies become more active at higher temperatures, while dangling bonds and charge traps on the STO surface affect carrier movement. Additionally, stress induced by differing thermal expansion coefficients of STO and MoS₂ at high temperatures contributed to decreased carrier mobility and increased SS.^38,39 Furthermore, temperature increase induced changes in the bandgap, shifts in the Fermi level, and alterations in the occupancy rate of interface trap states all contribute to the variation in threshold voltage.^39–42 The threshold voltage exhibited a linear correlation with temperature, with a coefficient of approximately −0.192.

Fig. 4 (a) Transfer characteristics of device 1 (D1) at different temperatures. (b) Changes in threshold voltage and carrier mobility with respect to temperature. (c) Comparison of D1 gate leakage current at room temperature versus at 100 °C. The inset displays the subthreshold swing at corresponding temperatures. Evolution of (d) transfer characteristics, (e) changes in threshold voltage and carrier mobility, and (f) gate leakage current and subthreshold swing of device 2 (D2) with storage time in ambient air at room temperature. The dark line shows the initial state of the device.

When the device was cooled back to room temperature, its transfer characteristics nearly matched those prior to heat treatment, with substantial recovery of SS, threshold voltage, and carrier mobility. This demonstrates that the monolayer MoS₂ did not suffer irreversible damage. Compared to the exposed MoS₂ FETs, the top STO encapsulation provided considerable protection effects.

Fig. 4e and f illustrate the long-term stability of the device. We stored device 2 (D2) in ambient air at room temperature for one month while measuring it every 10 days. The results indicate a largely stable performance, with only minor threshold voltage variations. The carrier mobility remained above 90% of its initial value after 30 days, while SS and leakage current (I_GS) remained virtually unchanged. These results further confirm the stability of STO encapsulated 2D transistors.

To further demonstrate the protective effect of the STO top gate, we fabricated monolayer MoS₂ transistors without STO using the same method and measured their temperature stability (Fig. S6) and long-term stability (Fig. S7). The measurement results show that for monolayer MoS₂ FETs without STO protection, the I_DS drops significantly and exhibits large hysteresis at 75 °C in an air environment, and obvious changes in transfer characteristics occur after being placed in the air environment for two weeks. For samples without STO protection, the temperature stability and long-term stability are far inferior to those for STO top-gated MoS₂ FETs.

Next, we measured the hysteresis effect in the STO top-gated MoS₂ FET with the V_DS fixed at 0.05 V throughout the measurement to ensure that the device operated in the linear region. We applied cyclic gate voltage bias to device 3 (D3), sweeping from negative to positive voltages and then back to negative. We progressively increased the V_GS sweeping range. Fig. 5a displays the measurement results in ambient air at room temperature. As is shown, D3 exhibited minimal clockwise hysteresis in lower voltage ranges, which gradually increased with the expanded sweeping voltage range. However, the I_GS remained almost unchanged, demonstrating the excellent dielectric strength of STO. Within a gate voltage sweeping range of −0.4 V to 1.0 V (sufficient for complete transistor switching), almost no hysteresis was observed, regardless of the V_GS sweeping direction (Fig. S8).

Fig. 5 (a) Transfer characteristics of device 3 (D3) in different V_GS sweeping ranges, with blue arrows indicating the V_GS sweeping direction. As the V_GS sweeping range increases, the hysteresis in I_DS becomes more pronounced. (b) and (c) Transfer characteristics of D3 at different V_GS sweeping speeds in different V_GS sweeping directions in the atmospheric environment. The V_DS sweeping in (b) is in the increasing direction. The V_DS sweeping in (c) is in the decreasing direction. Transfer characteristics of device 4 (D4) in the atmospheric environment after applying (d) a positive gate bias of +0.8 V and (e) a negative gate bias of for different durations. (f) A comparison of the SS and the I_on/I_off of transistors in our work with those of other top-gated monolayer MoS₂ FETs.^10,48–54 The materials of their dielectrics and the required voltages are also labelled.

Regarding electrical hysteresis in 2D FETs, gas adsorption and electron trapping at the channel material interface are commonly considered contributing factors.^15,43–47 To verify the cause of hysteresis in the STO top-gated MoS₂ FETs, we compared the transistor characteristics in a vacuum and in air, as shown in Fig. S9. The persistence of transfer characteristic hysteresis in a vacuum indicates that hysteresis is not solely caused by gas adsorption but likely results from multiple factors. Furthermore, we also performed similar measurements on monolayer MoS₂ FETs without STO (Fig. S10). The measurement results show that when there is no STO coverage, the hysteresis of monolayer MoS₂ FETs exhibited significant changes as the V_DS scanning range increased.

Low-rate V_GS sweeping is a common technique for analyzing FET hysteresis, as it provides sufficient time for gas adsorption/desorption and electron capture/release. To further analyze the hysteresis mechanism in the STO top-gated MoS₂ FETs, we measured the transfer characteristics of D3 under low-rate sweeping conditions in both air and vacuum environments. Fig. 5b and c present atmospheric measurements, while Fig. S11 shows the results obtained in a vacuum. These measurements revealed that when V_GS sweeping was performed under atmospheric conditions, the I_DS changes due to reduced measurement speed were significantly more pronounced than those in a vacuum, for both forward and reverse sweeping processes.

Furthermore, we also performed gate stress measurements on the STO top-gated MoS₂ FETs. For device 4 (D4) in both air and vacuum environments, constant bias voltages of +0.8 V or −0.8 V were applied for specific duration times, followed immediately by measurements of the transfer characteristics of the STO top-gated MoS₂ FETs using a constant sweep rate of 0.05 V s⁻¹. After each measurement, sufficient time was allowed before the next measurement to ensure complete device recovery. The measurement results are shown in Fig. 5d, e and Fig. S12. In the air environment, after applying positive gate pre-stress, the I_DS of D4 decreased significantly, with the magnitude of decrease increasing with longer pre-stress application time and gradually approaching saturation. When negative gate pre-stress was applied to the STO top-gated MoS₂ FETs, the I_DS increased with longer pre-stress application time.

Previous research has shown that when the V_GS exceeds 0 V, the adsorption of water and oxygen on MoS₂ gradually increases with prolonged positive gate bias until saturation occurs, resulting in carrier mobility degradation in the channel material. The slower the sweeping speed, or the longer the gate voltage bias time, the more pronounced the carrier mobility declines. This phenomenon is more evident during reverse sweeping than forward sweeping because during reverse sweeping, the gate is biased in the positive voltage range for a longer period earlier in the process, leading to faster impurity adsorption and more rapid carrier mobility reduction. When negative bias voltage was applied, the gradual desorption of water and oxygen molecules under the influence of the electric field resulted in the increase of I_DS. Although STO provides some encapsulation effect for MoS₂, as a crystalline oxide, it cannot achieve the absolute surface flatness characteristic of two-dimensional materials. Its surface consists of particulate undulations within the order of approximately 1 nm, creating microscopic gaps that render its isolation effect inferior to traditional 2D materials like BN.¹⁵

Measurements in a vacuum demonstrate that even after eliminating the adsorption effects of moisture and oxygen in the atmosphere, the impact of gate bias voltage stress on the STO top-gated MoS₂ FETs persists. Particularly in forward voltage sweep results, I_DS remains virtually unchanged with decreasing sweeping speed at negative gate voltages and small positive gate voltages. However, as V_GS gradually increases, carrier mobility begins to decline, with slower sweeping speeds resulting in more pronounced decreases.

For the gate stress tests, in the vacuum environment, although I_DS exhibited similar variation patterns in both positive and negative gate pre-stress tests, the magnitude was significantly smaller than the measurement results obtained in air. This indicates that adsorption and desorption of impurities such as oxygen and moisture in air constitute the primary cause of hysteresis, while charge trapping between the channel and the dielectric material also contributes, likely due to lattice defects and dangling bonds on the STO surface.²⁴ The presence of these interfacial defects will trap/release electrons under the action of gate voltage, leading to hysteresis in the transfer characteristics of FETs. Furthermore, for perovskite oxides such as STO, in addition to interfacial charge trapping, the electrostatic modulation effect caused by the migration of internal oxygen vacancies under an electric field should also be considered. In the stability study by Seyed et al.³¹ on few-layer MoS₂–STO back-gate FETs, the measured counterclockwise hysteresis was attributed to the diffusion of oxygen vacancies formed within the STO film during the growth process. In contrast, in our measurements, all devices exhibited clockwise hysteresis in both atmospheric and vacuum environments, indicating that oxygen vacancy diffusion is a secondary factor for STO top-gated monolayer MoS₂ FETs.

Furthermore, the effects of gate stress on I_DS are reversible upon removal of gate bias voltage. After applying the gate stress, we let D3 and D4 rest for 12 hours before remeasuring its transfer characteristics within a gate voltage sweeping range of −0.4 V to +1.0 V. As is shown in Fig. S13, the transfer curve was almost identical to the initial state, confirming that the monolayer MoS₂ did not suffer irreversible damage. Although gas adsorption and charge trapping at the MoS₂–STO interface led to some reduction in the stability of STO top-gated MoS₂ FETs against gate electrical stress, further hysteresis reduction would require improved device encapsulation and more compatible dielectric materials for MoS₂, such as introducing a BN buffer layer⁴⁷ between the MoS₂ channel material and STO. Additionally, the recoverability of STO top-gated MoS₂ FET hysteresis could be utilized for the fabrication of memory devices.

Fig. 5f shows the comparison of I_on/I_off and SS between the STO top-gated MoS₂ FETs in our work and other monolayer MoS₂ FETs using different dielectric materials.^10,48–54 The figure shows the types of gate dielectric materials and their required operating voltages. Our STO top-gated FETs, compared with other FETs, have high I_on/I_off and low SS, while their required operating voltage is very low, which enables them to operate under very low standby power consumption.

Conclusions

In this work, we fabricated high-performance monolayer MoS₂ FETs with an STO top-gate dielectric and measured their temperature stability, long-term stability, and electrical stress behavior. Experimental results demonstrate that the STO top-gated MoS₂ FETs maintained remarkably high stability under long-term storage conditions due to the encapsulation protection provided by STO top-gate dielectrics. Under high temperature and significant electrical stress, some degradation occurred, including carrier mobility reduction and increased hysteresis, which can be attributed to gas adsorption and charge traps at the channel–dielectric material interface. However, this degradation process is reversible and could be utilized for fabricating other functional electronic devices, such as memory and neuromorphic devices. Throughout the experimental process, the leakage current of STO as a dielectric material consistently remained at an exceptionally low level, confirming the immense application potential of STO for low power 2D FETs.

Author contributions

Y. R. L. and A. J. Y. contributed equally to this work. A. J. Y. and X. R. W. conceived the idea and designed the experiments. Y. R. L. and A. J. Y. fabricated the devices and performed the electrical measurements and analysis. L. W., S. H. W., H. P. H., and J. Y. Q. grew the STO. S. Y. X. performed the AFM measurements. Y. R. L., A. J. Y. and X. R. W. wrote the manuscript with the help of Z. W. L. and T. L. J. All authors contributed to the scientific discussion and commented on the manuscript.

Conflicts of interest

There are no conflicts to declare.

Data availability

Any additional information or materials associated with this study are available upon request to the corresponding authors.

The data supporting this article have been included as part of the SI. Supplementary information: Materials, devices fabrication, experimental techniques and further characterization data. See DOI: https://doi.org/10.1039/d5tc02024g

Acknowledgements

X. R. W. acknowledges support from the Singapore Ministry of Education (MOE) Academic Research Fund (AcRF) Tier 3 grant (MOE-MOET32023-0003) “Quantum Geometric Advantage” and Tier 1 (grant nos RG82/23 and RG155/24). L. W. acknowledges funding through the Xingdian Talent Support Project of Yunnan Province (Grant No. KKRD202251009) and Yunnan Fundamental Research Projects (grant no. 202201AT070171).

References

1. D. Akinwande, N. Petrone and J. Hone, Nat. Commun., 2014, 5, 5678.
2. M. Chhowalla, D. Jena and H. Zhang, Nat. Rev. Mater., 2016, 1, 16052.
3. A. D. Franklin, Science, 2015, 349, aab2750.
4. Y. Liu, X. D. Duan, Y. Huang and X. F. Duan, Chem. Soc. Rev., 2018, 47, 6388–6409.
5. K. Alam and R. K. Lake, IEEE Trans. Electron Devices, 2012, 59, 3250–3254.
6. W. Cao, J. H. Kang, D. Sarkar, W. Liu and K. Banerjee, IEEE Trans. Electron Devices, 2015, 62, 3459–3469.
7. S. Das, J. A. Robinson, M. Dubey, H. Terrones and M. Terrones, in Annual Review of Materials Research, ed. D. R. Clarke, 2015, vol. 45, pp. 1–27.
8. F. Hui, C. B. Pan, Y. Y. Shi, Y. F. Ji, E. Grustan-Gutierrez and M. Lanza, Microelectron. Eng., 2016, 163, 119–133.
9. K. K. Kim, A. Hsu, X. T. Jia, S. M. Kim, Y. M. Shi, M. Dresselhaus, T. Palacios and J. Kong, ACS Nano, 2012, 6, 8583–8590.
10. H. Y. Lan, S. H. Yang, K. A. Kantre, D. Cott, R. Tripathi, J. Appenzeller and Z. H. Chen, npj 2D Mater. Appl., 2025, 9, 8.
11. A. Facchetti, M. H. Yoon and T. J. Marks, Adv. Mater., 2005, 17, 1705–1725.
12. L. A. Majewski, R. Schroeder and M. Grell, Adv. Funct. Mater., 2005, 15, 1017–1022.
13. Y. S. Xu, T. Liu, K. L. Liu, Y. H. Zhao, L. Liu, P. H. Li, A. M. Nie, L. X. Liu, J. Yu, X. Feng, F. W. Zhuge, H. Q. Li, X. R. Wang and T. Y. Zhai, Nat. Mater., 2023, 22, 10.
14. Y. Y. Illarionov, A. G. Banshchikov, D. K. Polyushkin, S. Wachter, T. Knobloch, M. Thesberg, L. Mennel, M. Paur, M. Stöger-Pollach, A. Steiger-Thirsfeld, M. I. Vexler, M. Walt, N. S. Sokolov, T. Mueller and T. Grasser, Nat. Electron., 2019, 2, 230–235.
15. G. H. Lee, X. Cui, Y. D. Kim, G. Arefe, X. Zhang, C. H. Lee, F. Ye, K. Watanabe, T. Taniguchi, P. Kim and J. Hone, ACS Nano, 2015, 9, 7019–7026.
16. E. L. Hong, Z. Q. Li, X. Y. Zhang, X. S. Fan and X. S. Fang, Adv. Mater., 2024, 36, 9.
17. X. Y. Zhang, Z. Q. Li, E. L. Hong, T. T. Yan and X. S. Fang, Adv. Mater., 2025, 37, 12.
18. J. K. Huang, Y. Wan, J. J. Shi, J. Zhang, Z. H. Wang, W. X. Wang, N. Yang, Y. Liu, C. H. Lin, X. W. Guan, L. Hu, Z. L. Yang, B. C. Huang, Y. P. Chiu, J. Yang, V. Tung, D. Y. Wang, K. Kalantar-Zadeh, T. Wu, X. T. Zu, L. Qiao, L. J. Li and S. Li, Nature, 2022, 605, 262.
19. A. J. Yang, K. Han, K. Huang, C. Ye, W. Wen, R. X. Zhu, R. Zhu, J. Xu, T. Yu, P. Gao, Q. H. Xiong and X. R. Wang, Nat. Electron., 2022, 5, 233–240.
20. Y. H. Kim, H. J. Kim, M. Osada, B. W. Li, Y. Ebina and T. Sasaki, ACS Appl. Mater. Interfaces, 2014, 6, 19510–19514.
21. S. Y. Li, X. Y. Liu, H. Yang, H. Zhu and X. S. Fang, Nat. Electron., 2024, 7, 216–224.
22. B. K. Bussmann, O. Ochedowski and M. Schleberger, Nanotechnology, 2011, 22, 265703.
23. J. Y. He, Y. Zuo, T. Yang, T. Zhu and M. Yang, Front. Phys., 2025, 20, 014301.
24. A. J. Yang, S. X. Wang, J. W. Xu, X. J. Loh, Q. Zhu and X. R. Wang, ACS Nano, 2023, 17, 9748–9762.
25. A. J. Yang, L. Wu, Y. R. Liu, X. Y. Zhang, K. Han, Y. Huang, S. Y. Li, X. J. Loh, Q. Zhu, R. Su, C. W. Nan and X. R. Wang, Adv. Mater., 2023, 35, 2302620.
26. W. Z. Bao, X. H. Cai, D. Kim, K. Sridhara and M. S. Fuhrer, Appl. Phys. Lett., 2013, 102, 042104.
27. P. Bolshakov, P. Zhao, A. Azcatl, P. K. Hurley, R. M. Wallace and C. D. Young, Appl. Phys. Lett., 2017, 111, 032110.
28. Y. Y. Illarionov, G. Rzepa, M. Waltl, T. Knobloch, A. Grill, M. M. Furchi, T. Mueller and T. Grasser, 2D Mater., 2016, 3, 035004.
29. Y. Pan, K. P. Jia, K. L. Huang, Z. H. Wu, G. B. Bai, J. H. Yu, Z. H. Zhang, Q. Z. Zhang and H. X. Yin, Nanotechnology, 2019, 30, 095202.
30. Y. C. Sheng, X. Y. Chen, F. Y. Liao, Y. Wang, J. Y. Ma, J. N. Deng, Z. X. Guo, S. T. Bu, H. Shen, F. Y. Bai, D. M. Huang, J. L. Wang, W. D. Hu, L. Chen, H. Zhu, Q. Q. Sun, P. Zhou, D. W. Zhang, J. Wan and W. Z. Bao, Adv. Electron. Mater., 2021, 7, 2000395.
31. S. M. Sattari-Esfahlan, A. J. Yang, R. Ghosh, W. W. Zheng, G. Rzepa, T. Knobloch, M. Lanza, X. R. Wang and T. Grasser, ACS Nano, 2025, 19, 12288–12297.
32. H. L. Xu, Z. Y. Zhang, Z. X. Wang, S. Wang, X. L. Hang and L. M. Peng, ACS Nano, 2011, 5, 2340–2347.
33. A. Liu, X. Peng, S. Peng and H. Tian, IEEE Trans. Electron Devices, 2023, 1474.
34. B. Radisavljevic and A. Kis, Nat. Mater., 2013, 12, 815–820.
35. K. Kaasbjerg, K. S. Thygesen and K. W. Jacobsen, Phys. Rev. B: Condens. Matter Mater. Phys., 2012, 85, 115317.
36. N. Ma and D. Jena, Phys. Rev. X, 2014, 4, 011043.
37. X. L. Zou, Y. Y. Liu and B. I. Yakobson, Nano Lett., 2013, 13, 253–258.
38. Z. H. Cheng, C. S. Pang, P. Q. Wang, S. T. Le, Y. Q. Wu, D. Shahrjerdi, I. Radu, M. C. Lemme, L. M. Peng, X. F. Duan, Z. H. Chen, J. Appenzeller, S. J. Koester, E. Pop, A. D. Franklin and C. A. Richter, Nat. Electron., 2022, 5, 416–423.
39. K. K. H. Smithe, C. D. English, S. V. Suryavanshi and E. Pop, 2D Mater., 2017, 4, 011009.
40. B. W. H. Baugher, H. O. H. Churchill, Y. F. Yang and P. Jarillo-Herrero, Nano Lett., 2013, 13, 4212–4216.
41. L. T. Liu, Y. Lu and J. Guo, IEEE Trans. Electron Devices, 2013, 60, 4133–4139.
42. X. T. Sun, L. Xu, Y. Zhang, W. Z. Wang, S. Q. Liu, C. Yang, Z. Y. Zhang and J. Lu, ACS Appl. Mater. Interfaces, 2020, 12, 20633–20644.
43. T. Farooq, S. Sharma, S. Bhatt, S. Das and R. Mishra, J. Phys. D, 2025, 58, 055103.
44. Y. Guo, X. L. Wei, J. P. Shu, B. Liu, J. B. Yin, C. R. Guan, Y. X. Han, S. Gao and Q. Chen, Appl. Phys. Lett., 2015, 106, 103109.
45. F. B. Huang, Q. Y. Yang, Y. Y. Sun, J. H. Chen, C. X. Liu, Y. Chao, J. J. Hu, G. W. Hu and W. Huang, ACS Appl. Nano Mater., 2025, 8, 5805–5814.
46. T. Li, G. Du, B. S. Zhang and Z. M. Zeng, Appl. Phys. Lett., 2014, 105, 093107.
47. X. M. Zou, C. W. Huang, L. F. Wang, L. J. Yin, W. Q. Li, J. L. Wang, B. Wu, Y. Q. Liu, Q. Yao, C. Z. Jiang, W. W. Wu, L. He, S. S. Chen, J. C. Ho and L. Liao, Adv. Mater., 2016, 28, 2062.
48. W. S. Li, J. Zhou, S. H. Cai, Z. H. Yu, J. L. Zhang, N. Fang, T. T. Li, Y. Wu, T. S. Chen, X. Y. Xie, H. B. Ma, K. Yan, N. X. Dai, X. J. Wu, H. J. Zhao, Z. X. Wang, D. W. He, L. J. Pan, Y. Shi, P. Wang, W. Chen, K. Nagashio, X. F. Duan and X. R. Wang, Nat. Electron., 2019, 2, 563–571.
49. K. L. Liu, B. Fin, W. Han, X. Chen, P. L. Gong, L. Huang, Y. H. Zhao, L. Li, S. J. Yang, X. Z. Hu, J. Y. Duan, L. X. Liu, F. K. Wang, F. W. Zhuge and T. Y. Zhai, Nat. Electron., 2021, 4, 906–913.
50. B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti and A. Kis, Nat. Nanotechnol., 2011, 6, 147–150.
51. A. Rasyotra, M. Das, D. Sen, Z. Y. Zhang, A. Pannone, C. Chen, J. M. Redwing, Y. Yang, K. Jasuja and S. Das, ACS Nano, 2025, 19, 19646–19658.
52. A. Sebastian, R. Pendurthi, T. H. Choudhury, J. M. Redwing and S. Das, Nat. Commun., 2021, 12, 12.
53. Y. Q. Shen, S. Pazos, W. W. Zheng, Y. Yuan, Y. Ping, O. Alharbi, H. Liu, X. Lu and M. Lanza, ACS Nano, 2025, 19, 16903–16912.
54. Q. A. Vu, S. Fan, S. H. Lee, M. K. Joo, W. J. Yu and Y. H. Lee, 2D Mater., 2018, 5, 031001.

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Footnote

† These two authors contributed equally to this work.

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