Mass transport and grain growth enable high thermoelectric performance in polycrystalline SnS

Abstract

In polycrystalline SnS, the presence of grain boundaries inherently restricts the improvement of electrical performance, primarily owing to reduced carrier mobility. In this work, we employ grain boundary engineering to synergistically modulate carrier and phonon transport in SnS through the manipulation of mass transport dynamics linked to ramping and holding time-dependent grain evolution during pressure-assisted sintering. The pressure ramping process synergistically modulates grain distribution (grain boundary) and promotes mass transport (defect concentration), thereby jointly strengthening grain boundary and point defect phonon scattering, which reduces lattice thermal conductivity (κ_lat) by ∼30%. During the subsequent holding stage, optimized grain size evolution minimizes grain boundary potential barriers, reducing carrier scattering while elevating carrier mobility to ∼30 cm² V⁻¹ s⁻¹. Hall measurements and phonon frequency calculations corroborate the contributions of point defects and grain boundaries to κ_lat reduction, while microstructural characterization confirms that grain size optimization serves as the primary contributor to enhanced carrier mobility. Ultimately, the optimal sintering sample yields a low κ_lat of ∼1.2 W m⁻¹ K⁻¹ at 303 K and a maximum ZT of ∼0.8 at 873 K. Our findings highlight the feasibility of high performance polycrystalline SnS through grain boundary engineering, demonstrating its potential for cost-competitive and highly energy-efficient thermoelectric applications.

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1. Introduction

Thermoelectric materials, endowed with the capability to directly convert heat into electricity and vice versa,^1,2 have sparked considerable interest due to their promising potential in power generation from energy harvesting^3,4 and solid-state cooling through electrical current.^5,6 The energy conversion efficiency of a material is quantified by its dimensionless figure of merit, ZT = S²σT/κ_tot,^7–9 which relies on the optimal balance between high electrical conductivity (σ), large Seebeck coefficient (S), and low total thermal conductivity (κ_tot), where T represents the absolute temperature in kelvin. To enhance ZT, various strategies have been developed, including improving the power factor (PF = S²σ) through increased carrier concentration and mobility,^10,11 band convergence,^12,13 resonance levels,¹⁴ and band flattening,¹⁵ while reducing thermal conductivity via nanostructuring,¹⁶ all-scale hierarchical architectures,¹⁷ reduced electronic thermal conductivity (κ_ele)¹⁸ and seeking novel thermoelectrics with intrinsically low lattice thermal conductivity (κ_lat).^19–21

Although these strategic frameworks have guided thermoelectric research advances in classic systems like PbTe,^22–24 GeTe,^25,26 SnTe,²⁷ and PbSe,^28,29 their high-performance realization remains constrained by the parameter interdependencies, while the high cost impedes their commercial application.^30,31 Achieving superior thermoelectric performance in materials with intrinsically low κ_lat has emerged as an important research frontier in thermoelectrics, as it bypasses both the intricate intercoupling among thermoelectric parameters and the thermal stability issues inherent to nanostructured systems. Recent studies have emphasized SnSe as a highly promising thermoelectric material owing to its extremely low thermal conductivity, originating from strong lattice anharmonicity.^19,32 Moreover, its exceptional ZT benefits from the multivalley band structure and three-dimensional (3D) charge and two-dimensional (2D) phonon transport characteristics.³³ SnS, an isostructural analogue to SnSe, has garnered growing interest in thermoelectrics due to its promising practical applications, with non-toxic, low-cost and earth-abundant constituents.³⁴ Although the layered structure and low symmetry in the lattice endow it with low thermal conductivity, the electrical performance of SnS is poor owing to its large bandgap and strong ionicity (electronegativity) of sulfur.³⁵ To address these challenges, some efficient optimization strategies have been proposed, such as doping to increase carrier concentration,^36,37 textured microstructures³⁸ or crystal growth^39,40 to improve carrier mobility, and band engineering to balance carrier effective mass and mobility.⁴¹ Currently, SnS crystals have achieved significant progress, with a prominent ZT exceeding 0.5 at room temperature and a maximum ZT (ZT_max) of ∼1.6 at high temperatures.^41,42 Despite these advancements, SnS in the crystalline form still faces limitations in thermoelectric device applications, hindered by poor mechanical robustness and high production costs (crystal growth conditions are stringent and time-consuming).⁴³ Compared to crystalline counterparts, polycrystalline SnS exhibits significantly reduced carrier mobility and inferior electrical performance due to the presence of grain boundaries.³⁸ However, these drawbacks are partially offset by its lower thermal conductivity and superior mechanical and thermal stability. Therefore, achieving thermoelectric transport performance comparable to crystalline SnS remains a significant challenge for this system.

The most significant difference in transport properties between single-crystalline and polycrystalline SnS lies in lattice thermal conductivity (κ_lat) and carrier mobility (μ). Therefore, our investigation in this work focuses on the influence of grain boundary and grain evolution during the sintering process of polycrystalline samples on their thermoelectric transport properties (Fig. 1a). Through controlling ramp-up time of sintering pressure and holding time during the sintering process, it is found that these two processes modulate the κ_lat and μ of polycrystalline SnS samples, respectively. Specifically, controlling the sintering pressure ramp time to regulate the intergranular grain boundary enhances phonon scattering. Meanwhile, driven by concentration gradients or external stimuli (e.g., pressure and temperature), defect atoms can undergo diffusion migration at particle surfaces or within the bulk (i.e., mass transport).^44,45 This process, occurring at grain boundaries of SnS, increases the defect concentration, thereby further intensifying phonon scattering and reducing κ_lat. Additionally, adjusting the holding time to promote grain growth alleviates carrier scattering at grain boundaries, thereby boosting μ. When the sintering pressure ramp time was set to 11 minutes, the κ_lat of the sample decreased from ∼1.9 to 1.3 W m⁻¹ K⁻¹. Meanwhile, with a holding time of 12 minutes, the μ increased to ∼30 cm² V⁻¹ s⁻¹ (Fig. 1b). Ultimately, by modulating the pressure ramp-up stage to accelerate the formation of effective intergranular grain boundaries and mass transport and extending the holding time to promote grain growth, we achieved synergistic optimization of κ_lat and μ, bringing about a superior ZT value of ∼0.8 at 873 K (Fig. 1c).

Fig. 1 (a) Schematic diagram of the mass transport and grain growth processes in polycrystalline SnS during the sintering process. (b) Room-temperature thermal conductivity and carrier mobility of samples under different sintering conditions. (c) ZT values. The reported polycrystalline SnS-based materials are also plotted for comparison.^34,36,37

2. Results and discussion

SnS exhibits intrinsically low thermal conductivity, but its large bandgap and inherently low carrier concentration result in electrical transport properties deviating significantly from the optimal concentration regime. Commonly, Na doping is recognized as the most effective carrier concentration modulation strategy to boost the electrical performance of SnS.³⁵ Therefore, a series of Na contents are doped into Sn sites to synthesize polycrystalline Sn_1−xNa_xS (x = 0.3%, 0.5%, 0.7%, 1%, 2%) samples, and the optimal electrical transport sample is screened to investigate the impact of grain boundary engineering on its thermoelectric transport behaviors. As depicted in Fig. S1,† the 1% Na doped sample processes a high electrical conductivity of ∼60 S cm⁻¹ at room temperature. All samples exhibit larger Seebeck coefficients owing to the multi-valence band structure after increasing carrier density (Fig. S1b†).⁴² Hence, considering both two parameters comprehensively, the 1% Na doped sample stands out for its superior electrical performance (PF), which increases from ∼2.0 μW cm⁻¹ K⁻² at 303 K to ∼5.0 μW cm⁻¹ K⁻² at 873 K. To systematically study the influence of grains and grain boundaries on charge carriers and phonons, Sn_0.99Na_0.01S samples under varying sintering conditions are fabricated. As revealed by the X-ray diffraction (XRD) patterns, all the samples with different ramp-up and holding times during the sintering process exhibit uniform SnS single-phase nature with no additional peaks observed (Fig. S2†).

The sintering-induced grain coarsening dynamics in SnS powders are found to critically determine thermoelectric performance parameters. The thermal transport properties are predominantly governed by lattice contributions, rendering the charge carrier contribution negligible (Fig. S3†). Fig. 2a presents a comparative analysis of the lattice thermal conductivity for Sn_0.99Na_0.01S samples prepared under varying ramp-up times. The 11-minute (ramp-up) sintered sample shows a ∼30% reduction of κ_lat at 303 K compared to the 9-minute counterpart. Notably, this low thermal conductivity state persists across the 303–450 K temperature range, demonstrating significant phonon suppression associated with grain boundaries and point defects (Fig. 2b). This phenomenon arises from grain coalescence under applied pressure, where the formation of effective grain boundaries significantly modulates the κ_lat of sintered samples through enhanced phonon scattering at interfaces. Additionally, the mass transport process occurring at grain boundaries further increases defect concentration, thus reducing κ_lat. It can be observed that increasing the ramp-up time induces dynamic changes in the carrier concentration and mobility for the sample (Fig. 2c). The carrier density increases from ∼9 × 10¹⁸ cm⁻³ to ∼1.2 × 10¹⁹ cm⁻³, while the reduction in μ jointly corroborates the enhanced carrier-phonon scattering mechanism. Moreover, this sintering process slightly affects charge carrier transport. Compared to its contribution to thermal conductivity, the impact of ramp-up time on electrical transport properties becomes negligible, as evidenced by the consistent electrical transport properties demonstrated across all samples (Fig. 2d–f). Therefore, rational pressure regulation during sintering enables the formation of effective grain boundaries via intergranular contact and redistributes defect concentrations during mass transport, which synergistically enhance phonon scattering and substantially reduce κ_lat. While this process exerts negligible impact on electrical transport properties.

Fig. 2 Thermoelectric properties of Sn_0.99Na_0.01S with different ramp-up times. (a) Lattice thermal conductivity. (b) The spectral lattice thermal conductivity κ_s(ω) exhibiting contributions from various scattering sources, and the acoustic mode Debye frequency is ω_a. (c) Carrier concentration and mobility. (d) Electrical conductivity. (e) Seebeck coefficient. (f) Power factor.

To achieve further optimization of electrical properties, we systematically modulated the holding time to facilitate grain growth and consequently enhance carrier mobility. Fig. 3a–c comprehensively present the electrical transport characteristics of Sn_0.99Na_0.01S samples fabricated under different holding times. As evidenced in Fig. 3a, increasing the holding time yields a significant improvement in electrical conductivity (σ). Notably, the sample with a 12-minute holding time achieves a ∼50% improvement compared to the 10-minute counterpart at room temperature. The Seebeck coefficients for all samples demonstrate consistent values across the entire working temperature range (Fig. 3b). This trend aligns with the experimental Hall measurement results that the carrier concentration (n_H) remains unchanged (∼1.2 × 10¹⁹ cm⁻³) under extended holding time conditions, as illustrated in Fig. 3c. The Pisarenko plot indicates a constant effective mass of 0.63m_e for all samples (Fig. 3d). These results collectively demonstrate that the variations in electrical conductivity under extended holding time conditions primarily originate from the μ rather than the carrier density. The carrier mobility and corresponding electrical conductivity values of samples with holding times of 12 and 14 minutes exhibit a consistent trend. Notably, the 12-minute sample achieves a remarkable μ of ∼30 cm² V⁻¹ s⁻¹ at 303 K, which is significantly enhanced by nearly 50% compared to the 10-minute sample. The 14-minute sample also demonstrates a high μ of ∼26 cm² V⁻¹ s⁻¹, accompanied by enhanced electrical performance across the entire temperature range. This optimized sample achieves a high PF of ∼5.6 μW cm⁻¹ K⁻² at 873 K (Fig. 3e). Through weighted mobility (μ_w) calculation, the 12-minute sample achieves a room-temperature μ_w of ∼21 cm² V⁻¹ s⁻², representing the maximum value among all samples with different ramp-up and holding time conditions (Fig. 3f).

Fig. 3 Thermoelectric properties of Sn_0.99Na_0.01S with different holding times. (a) Electrical conductivity. (b) Seebeck coefficient. (c) Carrier concentration and mobility. (d) Pisarenko plot. (e) Power factor. (f) Weighted mobility.

To elucidate the underlying mechanism of electrical property optimization through holding time modulation, scanning electron microscope (SEM) characterization is systematically conducted on the 10-minute and 12-minute holding time samples, respectively. The SEM microstructures (Fig. 4a and c) reveal distinct grain boundary architectures between the two holding time conditions. The corresponding enlarged views clearly reveal that the 10-minute holding time sample (Fig. 4b) exhibits smaller grain sizes, whereas the 12-minute sample (Fig. 4d) demonstrates a notable increase in crystallite dimensions. Moreover, the EDS elemental mapping analysis confirmed homogeneous elemental distribution in Na doped SnS samples without secondary phases, consistent with XRD results. It should be emphasized that the 12-minute sample exhibits distinct microstructural advantages, including optimized grain morphology and reduced porosity, which demonstrates the effectiveness of extended holding time in promoting grain growth. Thus, the grain boundary engineering (12-minute holding time) enables precise grain size control and optimized carrier transport, simultaneously reducing grain boundary potential and mitigating carrier scattering, which collectively result in a ∼50% enhancement of carrier mobility (Fig. 3c).

Fig. 4 Electron microscopic analysis on Sn_0.99Na_0.01S. Microstructure, grain distribution, and corresponding elemental maps of Sn_0.99Na_0.01S under holding times of (a and b) 10 min and (c and d) 12 min.

The thermal conductivity of Sn_0.99Na_0.01S demonstrates minimal variation across different holding times, as shown in Fig. 5a. This phenomenon stems from the mean free path (MFP) of phonons in SnS being significantly smaller than its grain size, limiting the impact of grain growth on lattice thermal conductivity.⁴⁶ The quality factor (B) and the ratio of μ_w/κ_lat can represent the performance upper limit of a material, which is exclusively associated with the inherent electronic or atomic structure, remaining independent of carrier concentration and Fermi level position.⁴⁷ As demonstrated in Fig. S4 and 5b,† the Sn_0.99Na_0.01S sample processed with optimized sintering parameters (11-minute ramp-up and 14-minute holding time) exhibits significantly enhanced B and μ_w/κ_lat values across the entire temperature range, which arises from the synergistic effects of mass transport and the grain growth process. Notably, the 14-minute sample achieves superior thermoelectric performance and exhibits the highest μ_w/κ_lat values of ∼17 and ∼43 at 303 K and 873 K, respectively. Finally, a maximum ZT value of ∼0.8 and a prominent average ZT value of ∼0.33 are achieved through lattice thermal conductivity reduction via mass transport processes and electrical transport properties optimization by grain growth (Fig. 5c). It is worth noting that the best-performing sample also exhibits excellent thermal cycling stability and reproducibility (Fig. S5 and S6†). The SnS-based sample with optimal thermoelectric performance achieves a maximum theoretical conversion efficiency of ∼7% at 873 K with a cold side temperature of 303 K, demonstrating its significant potential for cost-effective and high-efficiency thermoelectric device applications (Fig. 5d).

Fig. 5 (a) Thermal conductivity of Sn_0.99Na_0.01S with different holding times. (b) The μ_w/κ_lat of Sn_0.99Na_0.01S under different processes. (c) ZT value of Sn_0.99Na_0.01S with different holding times. (d) Theoretical efficiency of Sn_0.99Na_0.01S under different processes at a cold-side temperature of 303 K.

3. Conclusion

In polycrystalline materials, grain boundary engineering is recognized as a highly effective strategy for modulating both carrier and phonon transports, thereby achieving enhanced thermoelectric performance. In this work, we achieve synergistic enhancement of thermoelectric transport properties through grain boundary engineering by tailoring grain distribution and size during the polycrystalline SnS sample sintering process. Specifically, pressure ramping time modulation promotes grain contact to form effective grain boundaries and induces mass transport-driven defect concentration increase, which jointly enhance grain boundary and point defect scattering intensity. This dual control reduces lattice thermal conductivity by ∼30% at room temperature. Subsequently, extended holding time facilitates grain growth, reducing carrier scattering at grain boundaries and elevating carrier mobility to ∼30 cm² V⁻¹ s⁻¹. Experimentally, the increase in carrier concentration validated by Hall measurements corroborates the redistribution of defect concentrations during the mass transport process. Microstructurally, the enlarged grain size distribution observed via SEM directly reveals grain growth. Therefore, the cooperation of mass transport and grain growth processes synergistically enhances the thermoelectric ZT value of polycrystalline SnS. The optimal sample, subjected to 11-minute pressure ramping and 14-minute holding time treatment, exhibits exceptional thermoelectric performance, achieving a maximum ZT of ∼0.8 at 873 K while maintaining an average ZT of 0.33 across the temperature range from 303 K to 873 K. Our research strategy demonstrates the feasibility of achieving synergistic optimization of thermoelectric transport through grain boundary engineering in polycrystalline SnS materials, while also providing a novel research perspective for performance optimization of other polycrystalline thermoelectric materials.

Data availability

The authors declare that all data supporting the findings of this study are available within the article and its ESI.† Additional raw data can be provided by the corresponding author upon reasonable request.

Conflicts of interest

The authors declare no conflict of interest.

Acknowledgements

This work was supported by the National Natural Science Foundation of China (22205032), the Young Elite Scientists Sponsorship Program by CAST (2022QNRC001) and the Open Project Program of the State Key Laboratory of Artificial Intelligence for Materials Science (2024B03). W. He would like to acknowledge the support of the “Bairen” Program from the University of Electronic Science and Technology of China.

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Footnote

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d5ta05300e

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