Dual-field plated β-Ga2O3 nano-FETs with an off-state breakdown voltage exceeding 400 V

Jinho Bae a, Hyoung Woo Kim b, In Ho Kang b and Jihyun Kim *a
aDepartment of Chemical and Biological Engineering, Korea University, Anamdong-5-Ga, Seoul 02841, South Korea. E-mail: hyunhyun7@korea.ac.kr
bKorea Electrotechnology Research Institute (KERI), Seongsan-gu, Changwon-si, Gyeongsangnam-do 51543, South Korea

Received 19th September 2019 , Accepted 8th January 2020

First published on 9th January 2020


The nature of ultra-wide energy bandgap (UWBG) semiconductors enables transistors to withstand large voltage swings, ensuring stable high-power and high-efficiency operation. The potential of UWBG β-Ga2O3 nano-field effect transistors (nano-FETs) has not been fully explored due to premature avalanche breakdown in these devices, despite their extremely high critical breakdown field. An exfoliated β-Ga2O3 nano-layer was fabricated into a depletion-mode nano-FET integrated with dual field-modulating layers to redistribute the electric field crowded around the drain edge of the gate electrode. A stepped-gate field-plate and a source-grounded field-modulating electrode were integrated into the planar β-Ga2O3 nano-FETs. Excellent output and transfer characteristics were demonstrated, i.e. a low subthreshold swing (95.0 mV dec−1) and high on/off ratio (∼1010), achieving an ultra-high off-state three-terminal breakdown voltage of 412 V. The experimental results were compared with numerical simulations, confirming the efficacy of the dual-field plate structure. The introduction of multiple field-modulating plates into the UWBG β-Ga2O3 nano-FETs greatly increased the voltage swings to over 400 V, suggesting the possibility for small footprint power electronics.


Introduction

Power electronic devices are essential building blocks for achieving efficient energy conversion and control in versatile applications such as electric power transmission, power distribution systems, and wireless communication systems. Due to government regulations and standards on energy and environmental issues, power devices are required to have improved efficiency and lower power loss. Silicon, which is a first-generation semiconductor, still plays a dominant role in power electronic devices. However, the relatively small bandgap of Si (1.1 eV) limits its applications. Alternatively, wide bandgap semiconductors, including gallium nitride (GaN), silicon carbide (SiC), and diamond, have been intensively investigated because they can tolerate higher power density with a superior breakdown field. AlGaN/GaN high electron mobility transistors with low switching loss have been commercialized for high-frequency and high-power applications.1,2 Recently, inverters based on SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) have been used in electric vehicles.3 Power electronics with a smaller footprint and lighter weight can be achieved by using wide bandgap semiconductors, which in turn lowers the operation cost.4

β-Gallium oxide (β-Ga2O3), which is an ultra-wide energy bandgap semiconductor (4.7–4.9 eV), is well known for its large breakdown field (∼8 MV cm−1 (estimated)) and high Baliga's figure of merit (3214.1), exceeding those of GaN and SiC. Single-crystalline substrates with diameters larger than two inches are commercially available, allowing strain-free β-Ga2O3 epitaxy on a wafer scale.5,6 Interestingly, β-Ga2O3 is advantageous for the miniaturization of electronic devices as its crystallinity is maintained after mechanical exfoliation.7,8 Mechanical exfoliation has been widely used in van der Waals materials to obtain crystalline nano-layers.9 Although β-Ga2O3 is not a van der Waals material, it can be separated into nano-layers due to the large anisotropy among the lattice constants, which is highly advantageous for device miniaturization.7 Various electronic and optoelectronic devices based on β-Ga2O3 nano-layers have been demonstrated, including MOSFETs, metal–semiconductor field-effect transistors (MESFETs), and solar-blind photodetectors.10–12 Nano-layered β-Ga2O3 can be integrated with Si and other two-dimensional van der Waals materials to fabricate hetero-structured (opto)electronic devices. A β-Ga2O3 flake-based deep-ultraviolet photodetector with a graphene gate electrode exhibited an outstanding photo-response owing to the high optical transparency of the graphene electrode.13 Kim et al. demonstrated a β-Ga2O3 junction FET through van der Waals bonding with an exfoliated p-WSe2 flake, which showed a high rectifying ratio and breakdown voltage.14

Electrical hard breakdown of electronic devices limits their performance and may eventually lead to catastrophic damage. Premature breakdown can originate from a localized electric field that exceeds the critical electric field due to the non-uniformity of the device structure and the non-optimization of the fabrication processes, where the origin of the electrical breakdown is attributed to the avalanche mechanism.2,15 Notably, the low thermal conductivity of β-Ga2O3 may increase the temperature of the channel layer, accelerating the carrier multiplication process. Therefore, various methods have been introduced to redistribute the locally concentrated electric fields by employing overlapped gate, field-plate, recessed-gate, and guard-ring structures because the electric fields are generally crowded at the edge of the gate electrode.16–19 Sharma et al. optimized the device structure for high-power devices based on thermal simulations of high-current β-Ga2O3 rectifiers.20 Yang et al. reported large-area, field-plated vertical β-Ga2O3 rectifiers with high forward current (1 A) and high reverse breakdown voltage (760 V).21 Wong et al. reported molecular beam epitaxy-grown β-Ga2O3 MOSFETs with an off-state breakdown voltage of 755 V, where a gate-connected field-plate structure and surface passivation layer were employed.22 However, the breakdown voltage of nano-FETs is still inferior to that of conventional thin film FETs due to the crowding of the electrical field. The field-modulating plate configuration has been rarely applied to nano-FETs. Here, we introduce a dual-field plate architecture to realize the full potential of β-Ga2O3 nano-FETs, where an overlapped gate and source field plates are both integrated with the nano-layered β-Ga2O3 channel. These structures can expand the voltage swing of the devices, improving the device performances and stability under high-power operation.

Experimental details

A single-crystalline β-Ga2O3 substrate (Tamura Corp.) with an effective carrier density of approximately 3.5 × 1017 cm−3, grown by the edge film growth method, was mechanically exfoliated into quasi-2D nanolayers using commercial adhesive tape. The exfoliated β-Ga2O3 nanolayer flakes were transferred onto a thermally grown SiO2 (300 nm)/Si (500 μm) substrate via a standard dry transfer method. Both the source and drain electrodes were defined using the electron beam lithography (EBL) technique. Ohmic Ti/Au metal electrodes (50 nm/100 nm) were deposited using an electron-beam evaporator. Rapid thermal annealing (Mila-5050, Ulvac Technologies, Inc.) under a low vacuum (<10 mTorr, N2 atmosphere) was performed at 500 °C for 1 min to improve the ohmic contact. Hexagonal boron nitride (h-BN) flakes were mechanically exfoliated from the bulk powder (Momentive Corp.) and dry-transferred onto the β-Ga2O3 channel at a specific position by using the transparent gel-film (Gel-pak)-assisted transfer method. Ni/Au (50 nm/100 nm) was deposited as the top-gate electrode of the β-Ga2O3 nano-FETs, and was defined by EBL to fabricate the gate field plate (GFP) structure. A SiO2 dielectric layer with a thickness of 200 nm was deposited using plasma-enhanced chemical vapor deposition (PECVD, VL-LA-PECVD, Unaxis), followed by patterning the source field plate electrode (SFP, Ti/Au (50 nm/100 nm)). The overall device fabrication process is shown in Fig. 1.
image file: c9tc05161a-f1.tif
Fig. 1 Fabrication procedure of the dual-field plated β-Ga2O3 nano-FET: (a) patterning of source and drain ohmic contacts onto the exfoliated β-Ga2O3 nano-layer, (b) deposition of 2D h-BN via a dry transfer technique, (c) patterning of a stepped gate (Ni/Au) electrode as the GFP, (d) deposition of a PECVD-SiO2 dielectric layer and (e) patterning of an SFP (Ti/Au) electrode.

The surface morphology and thickness of the fabricated dual-field plated devices were characterized using optical microscopy (Olympus, BX51M) and atomic force microscopy (AFM; Innova, Bruker). The structural properties of the exfoliated β-Ga2O3 and h-BN flakes were analyzed using micro-Raman spectroscopy in back-scattering geometry at a wavelength of 532 nm of a diode-pumped solid-state laser (Omicron). The cross-sectional device structure and crystal orientation of the exfoliated β-Ga2O3 and h-BN were investigated using scanning transmission electron microscopy (TEM, JEM-2100F, JEOL). The TEM specimen was prepared by using the focused ion beam (FIB) technique (Quanta 3D FEG, FEI). The surface of the specimen was protected from FIB damage by a carbon layer. The electrical properties of the field-plated β-Ga2O3 nano-FETs were determined using an Agilent 4155C semiconductor parameter analyzer connected to a probe station. The three-terminal off-state breakdown voltage of the fabricated nano-FETs were measured using a Keithley 6485 picoammeter connected to a Keithley 248 high-voltage supply. The devices under test were immersed in a Fluorinert solution (FC-40, 3M) to prevent unintended dielectric breakdown during high voltage measurements. The distribution of the electric field was numerically calculated by using the SILVACO Atlas device simulation software (ver. 5.21.1.R). The thermal distribution of the nano-FETs was simulated using finite element method software (FlexPDE (ver. 7.11)).

Results and discussion

The optical microscope image (Fig. 2(a)) and AFM image (Fig. 2(b)) of the representative β-Ga2O3 dual-field plate nano-FET are presented, where the thickness of the exfoliated β-Ga2O3 was 300 nm. Although β-Ga2O3 is not a van der Waals layered material, it can be separated into quasi-2D layers due to the large anisotropy of the monoclinic unit cell (a [100] = 12.225 Å, b [010] = 3.039 Å, and c [001] = 5.801 Å). β-Ga2O3 nano-layers (200–500 nm thick) were obtained via mechanical exfoliation, and the exfoliated layers with a channel length of 20–30 μm were fabricated into nano-FETs (Fig. 1(a)). The β-Ga2O3 nano-flakes separated from the single crystalline substrate had a root mean square value of less than 3 nm with a clean surface. H-BN, which has a van der Waals layered structure, is advantageous as a 2D dielectric layer due to the absence of surface charge and dangling bonds. H-BN flakes (30–50 nm thick) separated from the bulk crystal were aligned to a specific position of the β-Ga2O3 channel to utilize the h-BN layer as a GFP dielectric layer while maintaining its excellent physical and dielectric properties (Fig. 1(b)). The breakdown field of the h-BN, which has been widely used as a dielectric layer in 2D materials, is 8–12 MV cm−1, which is much higher than those of the conventional dielectric layers, including SiO2, Al2O3, and HfO2 (10, 7, and 5.4 MV cm−1, respectively).23–25 The high thermal conductivity (30 W K−1 m−1, out-of-plane) of h-BN also contributes to the stable operation of the device by dissipating the heat generated by Joule heating.26 A stepped gate structure was fabricated by partially depositing the gate electrode over the pre-deposited h-BN (Fig. 1(c)), followed by the deposition of a SiO2 passivation layer (Fig. 1(d)) and SFP electrode to complete the duel field-plate nano-FET (Fig. 1(e)). The Raman spectrum (Fig. 2(c)) was acquired to characterize the crystalline nature of each material at the overlapped layer of the h-BN GFP and the β-Ga2O3 channel of the fabricated device. Their phonon modes are well consistent with those of each single crystal (h-BN and β-Ga2O3), confirming the mechanical and chemical stability of each layer.27
image file: c9tc05161a-f2.tif
Fig. 2 (a) Optical microscopy image, (b) AFM image, and (c) Raman spectrum of the fabricated dual-field plated β-Ga2O3 nano-FET and (d) atomic structure of the β-Ga2O3 unit cell.

The cross-sectional TEM images of the dual field plated β-Ga2O3 nano-FET reveal the clean and flat interfaces of each layer, as shown in Fig. 3. It can be seen that the gate electrode (Ni/Au) conformally overlapped the ∼50 nm-thick h-BN GFP. The SFP overlapped the SiO2 layer without being disconnected, achieving a dual field-modulating architecture. The thickness and surface roughness of β-Ga2O3 and h-BN obtained from the TEM images are consistent with the AFM image (Fig. 2(b)). The high resolution TEM images of h-BN (Fig. 3(b)) and β-Ga2O3 (Fig. 3(c)) show that the device fabrication processes such as PECVD, heat treatment, and metal deposition did not affect the lattice structure of each material.


image file: c9tc05161a-f3.tif
Fig. 3 (a) Cross-sectional TEM image of the fabricated dual-field plated β-Ga2O3 nano-FET. Cross-sectional high-resolution TEM images of (b) h-BN and (c) β-Ga2O3.

A cross-sectional schematic of the fabricated dual-field plated β-Ga2O3 nano-FET is shown in Fig. 4(a). All electrical properties were measured with the SFP electrode grounded (connected to the source electrode). The DC output characteristics of the fabricated β-Ga2O3 nano-FET exhibited depletion-mode n-type characteristics with a large on/off ratio of ∼1010 (Fig. 4(b)), showing the possibility of high-performance and low-loss nano-electronics. More device results are available in the ESI. A linear increase was observed before the knee voltage. The output characteristics of the nano-FET showed excellent reproducibility under repeated measurements at VDS = +50 V, revealing the robustness of the β-Ga2O3 nano-FET under high bias conditions. The field-effect mobility (μFE) (Fig. 4(c)) was estimated by using the following equation:

image file: c9tc05161a-t1.tif
where gmax is the maximum transconductance, L is the length, W is the width, and d is the thickness of the β-Ga2O3 channel; q is the elementary charge and (Nd− Na) is the effective carrier concentration of the β-Ga2O3 channel. μFE was calculated to be 3.4 cm V−1 s−1, which is comparable to previous reports. The threshold voltage (Vth) was estimated to be −8.1 V by using the image file: c9tc05161a-t2.tifvs. VGS plot, as shown in the inset of Fig. 4(c). The low subthreshold swing (SS) of 95.0 mV dec−1 can be attributed to the h-BN dielectric with no surface charge and no dangling bond.


image file: c9tc05161a-f4.tif
Fig. 4 (a) Schematic of the dual-field plated β-Ga2O3 nano-FET. (b) DC output and (c) transfer characteristics of a representative dual-field plated β-Ga2O3 nano-FET. The inset shows a plot of image file: c9tc05161a-t3.tifvs. VGS. (d) Off-state three-terminal hard breakdown characteristic of the fabricated dual-field plated β-Ga2O3 nano-FET.

Under high electric field operation, a carrier with large kinetic energy collides with the lattice of the channel and transfers its energy, generating electron–hole pairs in the conducting channel. Then, the electron–hole pairs generated by this impact ionization promote a series of carrier multiplication steps, resulting in an increase in the off-state current. Large leakage currents can cause permanent damage to the device. A FET with high off-state breakdown voltage is required for power electronic devices in order to ensure stable operation under high-voltage conditions. Measurements of the three-terminal off-state breakdown voltage were performed under the pinch-off condition of VGS = −10 V, where the device under test was immersed in a Fluorinert solution to prevent dielectric breakdown due to unintentional ambient molecules. In the dual-field plate device, the three-terminal off-state hard breakdown voltage was measured to be VDS = +412 V, which is much higher than that of the conventional device without the field plate (+145 V), with a single h-BN GFP structure (+344 V), and with a single SFP structure (+314 V).12,28 High-voltage-tolerance electronic devices are advantageous because power supplies with a voltage of ∼400 V are widely used when converting from AC to DC for end users. In addition, hybrid or electric fuel cell vehicles have operating voltages of 150–400 V. The large improvement in the off-state breakdown voltage demonstrates the possibility of miniaturization of the power FET with a driving voltage of over 400 V.

The electric field distribution of the β-Ga2O3 nano-FET was numerically investigated by using the SILVACO device simulation software. Four β-Ga2O3 nano-FET devices with different structures were compared to assess the effects of the field plate on the spreading of the electric field: (a) no field plate, (b) only an SFP, (c) only a GFP, and (d) dual-field plates. Fig. 5 shows the electric field distribution of each device structure for a bias condition of VDS = +400 V. In the conventional device without the field plate (Fig. 5(a)), the peak electric field over 5 MV cm−1 is crowded on the gate edge (position x = 10 μm), which may lead to premature breakdown due to non-idealities such as defective sites. Nonetheless, the breakdown voltage of the conventional-structured β-Ga2O3 nano-FET is still higher than those of the GaN- and SiC-based nano-FETs owing to the low impact ionization coefficient of β-Ga2O3. The impact ionization coefficient of β-Ga2O3 is 1.07 × 103 cm−1 at the maximum electric field of 5.1 MV cm−1.29 The impact ionization coefficient of β-Ga2O3 under the same electric field is significantly lower than that of 4H-SiC (2.73 × 105 cm−1) or GaN (4.93 × 104 cm−1), which demonstrates the high-voltage swing capability of the β-Ga2O3-based nano-FETs. Re-distributions of the peak electrical fields were observed when an SFP (Fig. 5(b)) or a h-BN GFP (Fig. 5(c)) was introduced into the conventional β-Ga2O3 nano-FET, where the SFP edge and GFP edge were located at x = 15 μm and x = 5 μm, respectively. In the case of the dual-field plate (Fig. 5(d)) in which both the SFP and GFP are applied in the same device, the maximum electric field decreased to 3.5 MV cm−1, which is a 30% decrease compared with the device without the field plate. The field plate dispersed the high surface electric field of the β-Ga2O3 nano-FET and prevented premature breakdown, realizing the full potential of the β-Ga2O3 material properties. The simulation results of the thickness-dependent electrical properties and breakdown voltages are available in the ESI. Therefore, the dual-field plate structure greatly reduces the leakage current of the fabricated device and increases the off-state hard breakdown voltage, which secures high-voltage driving stability compared with the conventional structure.


image file: c9tc05161a-f5.tif
Fig. 5 (left) Schematics of a β-Ga2O3 nano-FET with (a) no field plate, (b) only an SFP, (c) only a GFP, and (d) dual-field plates. (right) Corresponding simulation results for each schematic diagram.

The thermal managements of the conventional and dual-field plated nano-FETs are compared in Fig. 6(a) and (b) by using the finite element method. The dual-field plate structure with h-BN (360 W K−1 m−1, in-plane) and the SFP metal electrode enhanced the heat dissipation in the β-Ga2O3, which suffered from a low thermal conductivity of 15 W K−1 m−1. The dual-field plate structure greatly enhanced the thermal dissipation, leading to a decrease in the temperature in the β-Ga2O3 channel by approximately 8%. The poor thermal conductivity of β-Ga2O3 can be mitigated through the integration with other materials such as AlN (285 W K−1 m−1) and diamond (2000 W K−1 m−1), which have high thermal conductivities.30,31Fig. 6(c) shows the simulated thermal distribution for the dual-field plated β-Ga2O3 nano-device fabricated on an insulating diamond substrate, exhibiting a temperature reduction of approximately 10%. The β-Ga2O3 nano-FET, which exhibits a breakdown voltage exceeding 400 V, proposes a light-weight and high-efficiency power electronic device with a small footprint.


image file: c9tc05161a-f6.tif
Fig. 6 Simulated heat distributions for (a) conventional and (b) dual-field plated β-Ga2O3 nano-FETs. (c) Simulated thermal distribution for a dual-field plated β-Ga2O3 nano-FET on an insulating diamond substrate.

Conclusion

A high breakdown voltage nano-FET device with an off-state hard breakdown voltage exceeding +400 V was demonstrated by introducing dual-field plates to a β-Ga2O3 nano-layer. Both β-Ga2O3 and h-BN were mechanically exfoliated with their crystallinity and properties maintained. The field effect mobility, SS, and on/off ratio of the fabricated device were 3.4 cm2 V−1 s−1, 95.0 mV dec−1, and ∼1010, respectively, exhibiting excellent n-type depletion-mode switching characteristics. Three-terminal off-state hard breakdown of the dual-field plated β-Ga2O3 nano-FET was observed at VDS = +412 V, which is superior to those in previously reported nano-devices. The effects of the electric field distribution and thermal management of the dual-field plate structure were numerically analyzed. The implementation of a β-Ga2O3 nano-FET with a small footprint, which can be driven at voltages higher than 400 V, paves the way for miniaturizing high-power high breakdown voltage electronics.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

The research at Korea University was supported by the National Research Foundation of Korea (2018R1D1A1A09083917) and the Korea Institute of Energy Technology Evaluation and Planning (KETEP) (20172010104830). The research at KERI was supported by the KERI Primary research program of MIST/NST (No. 20-12-N0101-12).

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Footnote

Electronic supplementary information (ESI) available. See DOI: 10.1039/c9tc05161a

This journal is © The Royal Society of Chemistry 2020