S.
Bebiche
^{a},
P. A.
Cisneros-Perez
^{b},
T.
Mohammed-Brahim
^{a},
M.
Harnois
^{a},
J.
Rault-Berthelot
^{b},
C.
Poriel
*^{b} and
E.
Jacques
*^{a}
^{a}Univ Rennes, CNRS, IETR-UMR 6164, F-35000 Rennes, France. E-mail: emmanuel.jacques@univ-rennes1.fr
^{b}Univ Rennes, CNRS, ISCR-UMR 6226, F-35000 Rennes, France. E-mail: cyril.poriel@univ-rennes1.fr
First published on 13th June 2018
The electrical stabilities of n-type Organic Field-Effect Transistors (OFETs) based on dihydroindeno[1,2-b]fluorene and dihydroindeno[2,1-b]fluorene derivatives have been studied. These OFETs incorporate epoxy-based photoresist SU-8 as the gate insulator. The comparison of the electrical stability through gate bias stress measurements as a function of voltage and temperature stress shows that the instabilities of these OFETs result from different phenomena. Different models have been used to analyse the instabilities of the devices and these are discussed. As the two molecules only differ by their geometry and their substitution, this study shows how slight structural modifications of the semiconductor molecular structure induce electrical instabilities in the corresponding OFETs arising from different features.
The present work aims to report our investigations on the electrical stability of n-type OFETs using as the active layer a new electron-poor material based on the association of a dihydroindeno[1,2-b]fluorene core and dicyanovinylene groups (molecule 1, Fig. 1). These OFETs use the epoxy-based photoresist SU-8 as the gate insulator. This choice is mainly driven by our need to achieve fully organic OFETs in the near future and to better understand the organic–organic interface, a key feature in this technology. Thus, OFET characteristics using (1) as the active layer have been compared to those using a structurally related material, dihydroindeno[2,1-b]fluorene (molecule 2, Fig. 1), previously reported in literature.^{18,23} The comparison of the electrical stability of these OFETs through gate bias stress measurements as a function of voltage and temperature stress shows that the instabilities result from different phenomena, namely the density defect creation and the charge trapping. Different models have been used to analyse the instabilities of the devices and are discussed. As the two molecules only differ in the geometry (syn for (2) and anti for (1)) and by the presence of pentyl side chains in (1), this work shows how slight structural modifications of the semiconductor molecular structure can induce electrical instabilities in the corresponding OFETs arising from different features.
Fig. 1 Molecules investigated in this work based either on a dihydroindeno[1,2-b]fluorenyl core (1) or a dihydroindeno[2,1-b]fluorenyl core (2). |
The synthesis of (1) starts with the Suzuki–Miyaura cross-coupling of diethyl 2,5-dibromoterephthalate (3)^{47} with commercially available 4-pentylphenylboronic acid (Pd(PPh_{3})_{4}, K_{2}CO_{3}, THF/H_{2}O) providing the corresponding terphenyl (5) with the ester groups on the central phenyl ring and in the ortho position of one phenyl unit (Scheme 1, top). Acid promoted (MeSO_{3}H) intramolecular Friedel–Crafts acylation^{23,48} of (5) at high temperature (120 °C) readily took place to give the 2,8-dipentylindeno[1,2-b]fluorene-6,12-dione (6) with 86% yield. It should be noted that (6) is soluble in common organic solvents and is more soluble than its non-substituted analogue indeno[1,2-b]fluorene-6,12-dione, previously reported in literature.^{49} With dione (6) in hand, a Knoevenagel condensation in the presence of malononitrile and pyridine was finally performed providing bisdicyanovinylene (1) with a good yield of 59% (see the Experimental section for synthetic details). One should note that this reaction does not use titanium tetrachloride, a Lewis acid frequently used to activate the carbonyl units in such a reaction.^{46,50} This route is easy to perform, efficient (overall yield of 43%) and allows a gram scale preparation of (1), which is a key feature for further device applications. The synthesis of (2) is based on a similar strategy from diethyl 4,6-dibromoisophthalate 7 and has previously been reported (Scheme 1, bottom).^{41}
The determination of the LUMO energy level was of particular interest for the purpose of this work based on n-type OFETs as a low LUMO energy level is a key feature for charge injection within such a device. The LUMO can be estimated by means of cyclic voltammetry as LUMO (eV) = −[E^{red}_{onset} (vs. SCE) + 4.4] (based on an SCE energy level of 4.4 eV relative to the vacuum), Fig. 2.^{51,52} In dichloromethane, the voltammogram of (1) displays two reversible waves with maxima recorded at −0.42 and −0.64 V vs. SCE. Thus, the LUMO energy level of (1) has been estimated at ca. −4.1 eV (E_{onset} = −0.30 V). This value appears to be very deep, highlighting the strong impact of the dicyanovinylene units on the dihydroindeno[1,2-b]fluorenyl core.^{53} As the LUMO level of (2) has been reported at −3.81 eV, one should note that it is lowered by 0.30 eV compared to that of (1). This difference can be assigned to the structural deformations of the π-conjugated core of (2).^{41}
Fig. 2 Cyclic voltammetry at 0.1 V s^{−1} in CH_{2}Cl_{2}/[NBu_{4}][PF_{6}] 0.2 M in the presence of (1) and a platinum disk working electrode. |
Transfer characteristics in the linear (V_{DS} = 10 V) and saturation (V_{DS} = 100 V) regimes of (1) and (2) based OFETs are presented in Fig. 3. The most important parameters, that is, the mobility μ_{FE}, the threshold voltage (V_{TH}), the subthreshold swing (SS), and the on/off values of the drain current I_{D} (I_{Don}/I_{Doff}) were extracted from the transfer characteristics in the linear and saturated regime and are gathered in Table 1.
Fig. 3 Transfer characteristics in the linear (V_{DS} = 10 V) and saturation (V_{DS} = 100 V) regimes of (1)-based OFETs (left) and (2)-based OFETs (right). |
Molecule | Regime | μ _{FE} (cm^{2} V^{−1} s^{−1}) | V _{TH} (V) | SS (V dec^{−1}) | I _{Don}/I_{Doff} |
---|---|---|---|---|---|
(1) | Linear | 0.005 | 26 | 1.3 | 4 × 10^{6} |
Saturation | 0.021 | 20 | 1.9 | 5 × 10^{5} | |
(2) | Linear | 0.0009 | 20 | 2.3 | 8 × 10^{4} |
Saturation | 0.002 | 17 | 3.2 | 7 × 10^{4} |
The threshold voltage values are similar for both OFETs, typically around 20 V. This value can, nevertheless, be considered as high. However, it is clear that both OFETs can operate at a lower voltage. Indeed, all previous parameters have been determined from the classical equations of MOSFETs (Metal Oxide Semiconductor Field-Effect Transistor), see eqn (4)–(7) in the experimental section. Although these equations are used for OFETs and more generally for disordered semiconductor-based transistors, they were initially established for single crystalline silicon MOSFETs. However, in MOSFETs, the swing off–on is very sharp with a subthreshold slope SS value below 100 mV dec^{−1}. For disordered material based FETs, the swing is very slow leading to operational transistors in the subthreshold regime. In other words, OFETs studied in this work could be polarized at values below the threshold voltage value.
The field-effect electron mobility of (1)-based OFETs in saturation was found to be 0.02 cm^{2} V^{−1} s^{−1}, being 10 times higher than that of (2)-based OFETs (0.002 cm^{2} V^{−1} s^{−1}). The value found for (1) appears to be interesting for a dihydroindenofluorene but remains lower than those recently reported for indeno[1,2-b]fluorenones bearing either S-butyl side chains (0.65 cm^{2} V^{−1} s^{−1})^{42} or thiophene units (0.12 cm^{2} V^{−1} s^{−1})^{44} with different device architectures. One can also note that the I_{Don}/I_{Doff} ratio is significantly higher for (1)-based OFETs compared to (2)-based OFETs both in the linear and saturation regimes (Table 1). These I_{Don}/I_{Doff} values obtained for (1)-based OFETs (4 × 10^{6}) appear promising for practical applications. Finally, the SS value of (1)-based OFETs (1.3 V dec^{−1} in the linear regime) is also appealing for circuits and again appear to be better than that of (2)-based OFETs (2.3 V dec^{−1}). The electrical quality of the insulator–semiconductor interface can be involved in the good SS value. All these features clearly highlight that switching from the syn geometry found in the previously reported dihydroindeno[2,1-b]fluorene core of (2) to an anti geometry in the present dihydroindeno[1,2-b]fluorene core of (1) coupled to the addition of pentyl side chains have beneficial effects on both the field-effect mobility, the I_{Don}/I_{Doff} ratio and the SS without negative consequences on V_{TH}.
It should be mentioned that the groups of Marks and Fachetti have reported a structurally related dicyanovinylene-dihydroindeno[1,2-b]fluorene semiconductor possessing dodecanyl chains on the central phenyl ring. This compound did not possess any FET activity.^{39} Thus, the shortening of the alkyl chains (from C12 to C5) and their shifts to the side phenyl rings has an impressive beneficial effect on the field-effect mobility.
It is important to stress that the present OFET structure (i) is nearly fully organic-based with only the electrodes made in an inorganic material and (ii) has no particular treatment on the electrode surface or on the gate insulator (before deposition of the active layer). With device engineering (such as the grafting of self-assembled monolayers of 4-(dimethylamino)benzenethiol on the electrodes as previously reported on structurally related semiconductors),^{17} we are convinced that the present performance of (1)-based OFETs can be increased in future work.
Although the mobility, the subthreshold slope, the threshold voltage and the I_{Don}/I_{Doff} ratio provide interesting information to compare organic semiconductors in an OFET, they are not sufficient to perfectly understand their behaviour in a circuit. The behaviour of the active layer under polarization is therefore crucial to further achieve a circuit and the electrical stability of OFETs is one of the central parameters for practical use.
We first focus on the electrical behaviour of OFETs under a low (V_{GSstress} − V_{TH} = 20 V, Fig. 4-bottom) and a high (V_{GSstress} − V_{TH} = 40 V, Fig. 4-top) gate bias stress, both being higher than the threshold voltage. This experiment, called gate bias stress, involves applying a high bias voltage on the gate electrode to maintain the OFET in the on-regime. The stress voltage is applied for a total duration of 3 hours. Drain and source electrodes are grounded in order to uniformly stress the channel. At regular intervals of time, the stress is removed and transfer characteristics are plotted.
For all experiments, we first note a significant shift in the threshold voltage (ΔV_{TH}) toward positive values (Fig. 4). This is a classical behaviour.^{20} ΔV_{TH} reaches its highest value during the first 20 minutes of stress and then gradually decreases.
At V_{GSstress} − V_{TH} = 40 V, we note for both OFETs that the maximum current (at V_{GS} = 60 V) decreases with the stress time whereas the threshold voltage increases (Fig. 4). For the (2)-based OFET, the maximum current decreases by 40% and the threshold voltage increases by 60%. Both variations are larger for (1)-based OFET. As the current decreases by 70% and the threshold voltage increases by 100%, from a molecular point of view, we hypothesize that the difference between the two molecules can be ascribed to the alkyl chains borne by (1). However, these gate bias stress effects deserve to be discussed in detail, see below.
At V_{GSstress} − V_{TH} = 20 V (Fig. 4, bottom), the same conclusions as those above exposed for V_{GSstress} − V_{TH} = 40 V can be drawn for both OFETs with a striking difference: ΔV_{TH} is strongly attenuated in the case of 2 whereas ΔV_{TH} remains almost identical in the case of 1. Thus, we note a different V_{TH} shift as a function of the stress applied. This led us to more precisely investigate this feature. Two different mathematical models (eqn (1) and (2)) are used herein to understand the gate bias stress variations presented above: a stretched exponential law (eqn (1)), which implies a defect density creation^{54} within the organic semiconductor and a charge carrier trapping law (eqn (2)) occurring inside the gate insulator.^{55}
In the case of defect density creation, the V_{TH} variation with the stress time t is described by a stretched exponential law:
(1) |
The stretched exponential law is usually involved in describing relaxation phenomena in glasses towards equilibrium under different stresses.^{56} This law was established considering a diffusion of specific particles in a material with randomly distributed energy states. These states are able to trap these particles (‘trapping sites’).^{57} In disordered materials, containing metastable states, some physical parameters such as conductivity,^{58} threshold voltage of FETs^{54} or magnetization^{56} evolve following a stretched exponential law. In amorphous silicon TFTs, this effect has been associated with a dispersive diffusion coefficient of atomic hydrogen.^{54} This dispersion comes from the nature of any disordered material in which the trapping sites present a distribution of energy states. The β parameter in eqn (1) is related to this distribution of states and to the temperature. Most of the time, this law is efficient for describing the effect of any applied stress in a wide panel of situations. In single crystalline silicon-based MOSFET^{59} and polycrystalline silicon TFTs, the V_{TH} shift is related to the disordered gate insulator/active layer interface. In this case, the dispersive diffusion within the gate insulator/active layer interface (disordered material) can be involved. In disordered materials in general, any energy absorption inducing new charge carrier distribution can change the state of the weakest bonds, thus disturbing the equilibrium. The deformation can diffuse through the material leading to a new equilibrium state characterized by new defect distribution.
To explain the effect of the gate bias stress, another explanation involves a charge carrier trapping inside the gate insulator.^{55} This carrier trapping can be negligible in most OFETs that use inorganic silicon dioxide as the gate insulator. However, since the present gate insulator is an organic material i.e. SU8 photoresist, the trapping model deserves to be precisely investigated. This model involves an injection of carriers inside the insulator due to the applied gate bias stress. These carriers are trapped inside the insulator, fixing an electrical charge, which creates an opposite electric field near to the channel. Consequently, the effective gate voltage changes and induces the charge accumulation in the channel, leading to drain current variation. The threshold voltage variation is described by a logarithmic stress time dependence:^{55}
(2) |
In order to investigate which model can be used in the present case, two values for gate bias stress (V_{GSstress} − V_{TH} = 20 V or 40 V) and two different temperatures (30 and 40 °C) for both (1)- and (2)-based OFETs were investigated. The purpose is to favour the defect density creation and to evaluate the effect of the stress temperature.
We first started with a stress applied on the known compound (2) at a low-stress voltage, V_{GSstress} − V_{TH} = 20 V and for 2 different temperatures, 30 °C and 40 °C (Fig. 5a). The threshold voltage behaviour of these OFETs during the stress was successfully fitted by the stretch exponential model, i.e., eqn (1), describing the defect density creation (correlation factors are 0.995 and 0.991 at 30 °C and 40 °C respectively). The values obtained (β = 0.18 and t_{0} = 5.5 × 10^{3} s at 30 °C and β = 0.28 and t_{0} = 2 × 10^{3} s at 40 °C) appear to be similar to those reported in literature for amorphous silicon FETs;^{61} as expected, β increases and t_{0} decreases with the temperature. The maximum V_{TH} shift increases with the temperature, which is a coherent feature since trapping is enhanced when a higher density of carriers is generated in the channel. One can conclude that the stretch exponential model is suitable for the present stress and the V_{TH} shift could be attributed to defect density creation in the active layer. However, fitting the same experimental curves, with eqn (2) corresponding to the trapping model, attenuates this assignment. Indeed, Fig. 5b shows the same experimental curves as those presented in Fig. 5a but fitted with the trapping law (eqn (2)). It is clear that both experimental curves at 30 and 40 °C are also well fitted by this relation, with r_{d} = 3.82 and t_{0} = 0.4 s at 30 °C and r_{d} = 5.7 and t_{0} = 3.3 s at 40 °C (correlation factors are 0.995 and 0.992 at 30 °C and 40 °C respectively).
Fig. 5 Evolution of ΔV_{TH} with the stress time for (2)-based OFETs under V_{GSstress} − V_{TH} = 20 V at 30 °C and 40 °C. (a) The dashed lines are the fit with stretched exponential eqn (1). (b) The dashed lines are the fit with logarithmic eqn (2). |
To conclude, both experimental curves were well fitted by both the eqn (1) and (2), describing respectively the defect density creation inside the active layer and the carrier trapping at the gate insulator. The correlation coefficients are nearly the same. This fit alone does not allow discrimination between the two models and a possible explanation is that both phenomena simultaneously occur in the present stress conditions. This statement has also been observed when using different insulator layers to understand the dominant effect of threshold voltage shift.^{62}
Interestingly, the investigations of (1)-based OFETs in identical experimental conditions (V_{GSstress} − V_{TH} = 20 V) provide very different results. Indeed, attempts to fit the V_{TH} shift with the stretched exponential law (eqn (1)) failed and on the contrary, the fit with trapping law (eqn (2)) succeeded (Fig. 6a). The correlation factor is 0.996 and the parameters r_{d} and t_{0} are 10.7 and 28.8 s respectively at T = 30 °C. One can, therefore, conclude that the instability of (1)-based OFETs under low gate bias stress arises from carrier trapping occurring inside the gate insulator. This is a different behaviour from that exposed above for (2).
Fig. 6 (a) V_{TH} shift with the stress time under V_{GSstress} − V_{TH} = 20 V for (1)-based OFETs. Red dashed lines correspond to fit with logarithmic eqn (2) and blue dashed lines correspond to fit with stretched-exponential eqn (1). (b) Gate leakage current in (1) and (2)-based OFET. |
In conclusion, under low gate bias stress (20 V), the V_{TH} shift of (2)-based OFETs seems to be due to both the defect density creation inside the active layer and the carrier trapping inside the gate insulator. On the contrary, the V_{TH} shift of (1)-based OFET seems to be entirely due to the carrier trapping in the insulator. This indicates not only the better stability of the semiconductor (1) under electrical stress but more importantly, a very different trapping behaviour compared to its structural analogue (2). This observation could be argued based on a higher gate leakage current in (1)-based OFETs (Fig. 6b) compared to (2)-based OFETs, increasing the probability to trap charges in the insulator. From a molecular point of view, switching from syn geometry in 2 to anti geometry in 1 and introducing pentyl side chains has significantly changed the origin of the OFETs electrical instabilities. The origins of these electrical instabilities come from a different insulator/semiconductor interface. This work shows how slight structural modifications of the molecular structure of the semiconductor can lead to different insulator/semiconductor interfaces and thus to electrical instabilities arising from different features. Interface effects on the electrical instabilities have previously been approached by Ahmed et al.^{63,64}
In a second step, similar studies were performed by increasing the gate bias stress (V_{GSstress} − V_{TH} = 40 V) of (1) and (2)-based OFETs. The goal was to investigate the influence of the gate bias stress on the origin of the instabilities. This should lead to prominent trapping as tunnelling phenomena such as Fowler–Nordheim tunnelling generally occur at high applied voltage.^{57} For both (1) and (2)-based OFETs, the experimental curves are well-fitted (Fig. 7a) exclusively by eqn (2) and not by eqn (1). One can, therefore, conclude that at a high-stress voltage, the V_{TH} shift of both (1) and (2)-based OFETs follow the same trapping law.
Fig. 7 (a) V_{TH} shift with the stress time for (1) and (2)-based OFETs under V_{GSstress} − V_{TH} = 40 V. The dashed lines correspond to the fit with logarithmic eqn (2). (b) The ratio is a function of stress time for (1) and (2)-based OFETs under V_{GSstress} − V_{TH} = 40 V. |
In order to highlight this phenomenon, the ratio between the current variation and the V_{TH} shift is plotted in Fig. 7b as a function of the stress time for both OFETs. At constant V_{GS}, fixed at 60 V, and constant V_{DS}, fixed at 10 V, the ratio of current variation to threshold voltage shift is given by the following:
(3) |
Finally, the V_{TH} shift difference between (1) and (2)-based OFETs should be explained. As mentioned above, the V_{TH} increases by 100% for (1)-based OFETs and only by 60% for (2)-based OFETs after 3 hours of V_{GSstress} − V_{TH} = 40 V stress (Fig. 4). To explain the difference, the phenomenon of charge injection through tunnelling effects responsible for the carrier trapping can be involved. Here, the injected current is the leakage gate current I_{G} in the gate insulator. The variation of the trapped charges ΔQ is proportional to the injected current in the insulator. Due to the screening of previously trapped charges, the injected current decreases during the stress. The variation of these trapped charges is found to be responsible for the V_{TH} shift (ΔV_{TH} = −ΔQ/C_{insulator}). With this explanation, the gate leakage current is expected to decrease during the gate bias stress. In this case, its decrease is expected to be proportional to V_{TH} shift. Fig. 8 shows the decrease in the gate leakage current with the stress time for (1)-based OFETs. Plotting I_{G} current as a function of V_{TH} shift confirms the linear dependence between these two parameters (Fig. 8b). Therefore, Fig. 8 confirms that the effect of gate bias stress on (1)-based OFETs is due to carrier trapping inside the gate insulator. More generally, we can expect a significant V_{TH} shift depending on the initial value of the gate current in the case where the carrier trapping phenomenon is involved. Thus, the larger V_{TH} shift observed for (1)-based OFETs compared to (2)-based OFETs, under the same gate bias stress, could be explained by the higher gate leakage current initially observed in the device (Fig. 6b).
More importantly, we have surprisingly shown that the threshold voltage shift of the OFETs based on these two structurally related molecules arise from different features. Indeed, at low gate bias stress, the carrier trapping inside the insulator well explains the instability of (1)-based OFETs, whereas for (2)-based OFETs both the carrier trapping inside the insulator and the defect density creation inside the active layer can be involved. At high gate bias stress, the situation is again different as only the carrier trapping inside the insulator is involved for both (1) and (2)-based OFETs.
In addition, this work has also shown that (1)-based OFET displays a larger V_{TH} shift than (2)-based OFET (under the same gate bias stress), which has been assigned to a higher gate leakage current in the former. This feature can be related to the different insulator/semiconductor interfaces. Thus, this work shows how slight structural modifications of the molecular structure of the semiconductor can induce electrical instabilities of the corresponding OFETs arising from different features.
Compound 2 was synthesized according to literature procedures with spectroscopic analyses and purity in accordance with those of our previous works.^{41} The optical and electrochemical properties of 2 can be found in our previous works.^{41}
Compound 1 was synthesized as presented below.
Devices were stored and characterized in a glove box under ambient nitrogen. All electrical characterizations were performed using a Keithley 2636A. Transfer characteristic I_{D}–V_{GS} were plotted at room temperature. All the measurements were made under the same conditions, the gate-source voltage V_{GS} was varied from −20 V to 60 V with a 0.5 V step, at constant drain–source voltage V_{DS} (+10 V or +100 V). The procedure allows us to plot the transfer characteristics in linear and in saturation regimes.
Electrical parameters of both OFETs types in linear and saturation regimes have been summarized in Table 1. As usual, equations for MOSFETs have been used in both regimes. The drain current I_{D} in linear regime (V_{DS} ≪ V_{GS} − V_{TH}) is given by
(4) |
(5) |
The threshold voltage V_{TH} is the gate voltage axis intercept of I_{D}–V_{GS} curve plotted in linear representation. The field-effect mobility μ_{FE} is deduced from the extraction of g_{m}. The given value in Table 1 is the maximum value of μ_{FE}. The sub-threshold swing SS was extracted from the I_{D}–V_{GS} curve plotted in the semi-logarithmic scale using relation 6.
(6) |
In the saturation regime (V_{DS} ≫ V_{GS} − V_{TH}), the drain current is given by
(7) |
In this case, the slope of the square root of I_{D} as a function of V_{GS}, Wμ_{FE}C_{ins}/L, will give the mobility μ_{sat} in the saturation regime. The threshold voltage V_{TH} is the gate voltage axis intercept of the I_{D}^{1/2}–V_{GS} curve.
Footnotes |
† Electronic supplementary information (ESI) available. See DOI: 10.1039/c8qm00193f |
‡ Note that the corresponding 2,8-dipentyl-dihydroindeno[2,1-b]fluorene/dicyanovinylene has also been synthesized and studied in the course of this work. The electron mobility has been evaluated at 1.09 × 10^{−4} cm^{2} V^{−1} s^{−1} but the corresponding OFET does not present stable transfer characteristics. This instability does not allow the study of these OFETs in detail (see ESI† for the synthesis, properties and incorporation of 2,8-dipentyl-dihydroindeno[2,1-b]fluorene/dicyanovinylene) in OFETs. |
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