Direct growth of few layer graphene on SiO₂ substrate by low energy carbon ion implantation

Abstract

A simple method that enables the direct fabrication of few layer graphene on SiO₂/Si substrates by implantation of C ions is explored. The C ions of 80 keV with the fluencies of 1.2 to 2 × 10¹⁶ ions per cm² were implanted under the high vacuum directly onto the 200 nm thick Ni film deposited on SiO₂/Si substrates. The growth proceeds via the dissolution of C atoms into bulk Ni film that diffuse out towards both sides of Ni surface and pushing the C atoms to precipitate out by rapid annealing and cooling. As a result, the graphene growth takes place both on the top of the Ni film and at the interface of Ni/SiO₂ film. This direct synthesis of the graphene on SiO₂ is achieved by etching out the top Ni film. Raman and X-ray photoelectron spectroscopy investigations provide an evidence of strong resilience of the graphene to ion implantation. These results demonstrate that the feasibility C ion implantation technique is a viable route to define graphene directly on insulating substrates with controlled thickness for electronic device applications.

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1. Introduction

Graphene, a two dimensional monolayer of sp² bonded C atoms, has potential for high speed electronics due to its exceptional properties including high intrinsic electron mobility (200 000 cm² V⁻¹ s⁻¹) with zero band gap, and electric field doping. In the years since the first graphene was peeled off from highly oriented pyrolytic graphite by simple mechanical exfoliation,¹ various techniques have been emerged to synthesize graphene including chemical vapor deposition (CVD) on catalytic transition metals (such as Cu, Ni, Co and etc.),² epitaxial growth of graphene on SiC by thermal³ and electron beam treatment,^4–6 and certain chemical methods.⁷ Although, the most promising and inexpensive method, CVD offers meter scale production of graphene on transition metals such as Ni, Pd, Ru, Ir and Cu, the current limitation is that it is required to be transferred onto various substrates which is little incompatible for graphene electronics as it is shown to adversely affect the graphene structure.² Direct conversion of SiC into homogeneous epitaxial graphene through Si sublimation that can produce wafer scale graphene with high quality but suffers with high cost which making us to incredibly difficult to use it for low cost applications.^3–6,8 Moreover, graphene prepared from mechanical exfoliation and certain chemical methods are not suitable for electronic applications due to their low yield and structural defects, respectively. Besides, the nature of the underlying substrate seemed to possess a significant impact on the properties or applications of graphene electronics. A graphene layer on dielectric material is necessary to realize the unique properties of graphene that takes the advantageous when one wants to use graphene as component in various devices such as field effect transistors and quantum interference devices.⁸

Even though it is challenging, a few methods have been developed so far for the fabrication of few layered graphene on transition metal deposited dielectric substrates (SiO₂, h-BN) using hydrocarbon gases as a carbon feedstocks by CVD.^9–13 In these techniques, the hydrocarbon gases can be decomposed and dissolved on transition metals at elevated temperatures and the formation of graphitic layer is the direct consequence of precipitation and segregation of C atoms from bulk to surface of the transition metals through annealing and cooling. In addition, various sources such as any type of solid carbon sources and amorphous carbon have been explored to synthesis graphene.^14,15 The direct configuration of graphene for applications was then achieved by removing the metal films using etching process. However, several critical issues relating to yield, controlling the thickness of graphene, especially on metals having high C solubility, such as Ni, Co and Ru, are still to be refined before to realize graphene as an ideal candidate for microelectronics applications.

Ion implantation, a matured and routine technology, which has been developed by the semiconductor industry for the past three decades and is recently engaged for the synthesis of graphene over wafer scale.^16,17 This technique is widely employed to dope the source and drain contact regions and define the channel characteristics of CMOS transistors. But for graphene synthesis, this method utilizes C ions as feedstock that are implanted on transition metal supports and promotes direct growth of graphene with precisely controlled kinetics and thickness upon rapid thermal annealing. Ion implantation of C offers more appreciable benefits than CVD growth of graphene using hydrocarbon gases, where the high C solubility and diffusivity nature of catalytic metals making the controlled growth of CVD is challenging one.¹⁷ Utilizing ion implantations one could control easily and manipulate the carbon atoms with desired projected range by tuning the incident energy of the ion beams. This allows to exclude the uncertainties concerning about the amount of carbon ions are incorporated in to the Ni film and the number carbon atoms are diffused out upon rapid thermal annealing and cooling. Obviously, as the implanted fluence of C ions is precisely tunable, the thickness of the graphene layer are well controllable to maximum extent. To date, some groups have developed for the growth of graphene using C ion implantation.^17–24 In particular, Mun et al. have shown the local growth of graphene on SiO₂ substrates with a high mobility of 2900 cm² V⁻¹ s⁻¹.¹⁸ Kim et al. demonstrated wafer scale growth of graphene by high temperature C ion implantation.¹⁹ Zhang et al. have grown few layer graphene directly on SiO₂ substrates by negative C ion implantation.²⁰ All these above reports show the controlled and large area graphene growth utilizing ion implantation technique at different temperatures, but none of them have all the advantages. It is therefore strategically important to combine all these and yet there is no clear understanding about the mechanism that rules the graphene growth on dielectric substrate by ion implantation for practical applications.

In the present work, we explore a novel method for the fabrication of bilayer and few layers graphene with precise control of layer thickness by implantation of C ions.

2. Experimental techniques

Prior to the C ion implantation, a thin film of Ni with ∼200 nm was deposited on SiO₂ by electron beam evaporation which acts as a catalyst for the graphene growth. The surface morphology of the as-deposited Ni film was quite uniform on SiO₂ with an average grain size of ∼30 nm and the thickness variation was found to be ∼5 nm over the entire surface. Subsequently, low energy C ions were implanted into the Ni films with energy of 80 keV for a series of fluencies between 1.2 and 2.0 × 10¹⁶ ions per cm², which approximately corresponds to 4–5 mono atomic layer of surface C atoms, under a high vacuum of 10⁻⁶ mbar. The projected range of 80 keV C ions in Ni is ∼100 nm as calculated by SRIM (Stopping and Range of Ion in Matter). The implanted samples are subjected to ex situ high vacuum rapid thermal annealing of 700 °C and 1000 °C for 1 hour and cooled rapidly with a rate of 50 °C min⁻¹ to promote the growth of graphene layers. The surface features of the graphene were examined using field emission scanning electron microscopy (FESEM-Carl Zeiss-Σigma). Stacking of layers was confirmed by micro-Raman spectra recorded in the back scattering geometry using Lab Ram HR800 Raman spectrometer with an excitation wavelength of 632.8 nm. X-ray photoelectron spectroscopy (XPS) spectra were performed to identify the bonding nature of the graphene using excitation photon energy of Al K_α 1486.7 eV.

3. Results and discussion

The mechanism of growth of graphene by C ion implantation involves several stages such as out diffusion of implanted C followed by segregation and precipitation at the Ni surface upon rapid thermal annealing and cooling, which facilitates the formation of graphene layer as shown in the schematic diagram of Fig. 1. The implanted C ions get dissolved into the bulk Ni film as a result of rapid annealing at high temperatures (typically 700 °C and 1000 °C) for 1 hour. As the solid C solubility reduces upon cooling and/or the solid solution gets saturated at the growth temperature, the graphene growth proceeds via segregation and precipitation of C atoms on the metal surfaces. The thickness of the C layers can be precisely controlled by amount of dissolved C atoms when the metal that dissolves the C in its bulk can precipitate more substantial amount of C to the metal surface, leading to the controlled growth of graphene. Obviously, a precise control of layer thickness is possible since we can limit the amount of dissolved C atoms by tuning the number of implanted ions.

Fig. 1 Schematic diagram describing the growth mechanism of graphene by C ion implantation.

The C atoms has temperature dependent solubility in Ni which is known to play an important role in determining the growth of graphene layers. To probe the role of temperature, two different batches of samples were tested on the growth of graphene by C ion implantation, typically for 700 °C and 1000 °C.

The C solubility in Ni at different temperatures can be calculated using the formula of Lander et al.,^17,25,26

where S is the C solubility in weight% of C in Ni. One can derive the number of C atoms per cm³ using this equation,

Using eqn (2), the C solubility of ∼2.3 × 10¹⁵ and 4 × 10¹⁵ atoms per cm² in 200 nm thick Ni film at 700 and 1000 °C, respectively were deduced. These values are nearly equal to one C monolayer density (3.8 × 10¹⁵), implying that a graphene monolayer density can be diffused out onto the Ni surface, resulting in the controlled growth of graphene by surface limited process but driven by Ni grains upon cooling.

During rapid thermal annealing and cooling, the graphene films were found to grow on both atop of the Ni film and along the interface of the Ni and SiO₂ (as evidenced from Raman spectra). Because, the thermal treatment after implantation diffuse the C atoms towards the top of the Ni and at the interface between Ni and substrate depending on the energy of the implanted ion, C solubility and diffusion of C into Ni films. The implanted ion fluence corresponds to 4–5 monolayer thickness of graphene, however, the precipitation of C atoms occur on the both sides of the Ni surface. Indeed, the thickness and uniformity of the C layer is defined via the amount of C atoms diffuse out from each side of the Ni film. Furthermore, it has been shown that experimental facts involved in each steps i.e., during Ni evaporation on SiO₂ substrates, C implantation at room temperature and post annealing treatment could add some amounts of C atoms,²² which results in excessive growth of graphene with that of implantation fluence density of C atoms. However, we presume that, though the extra C atoms absorption from the environment is inevitable, it does not ensure the formation of graphitic structure as evidenced by Raman. The thickness of graphene layers formed on either side of Ni film can be well controlled and occasionally yield an additional thickness of one to two graphene monolayers, but primarily depending on the amount of out diffused C atoms from bulk Ni to the surface.

Upon annealing, Ni thin films form island-like 3D grains with heterogeneous distribution due to the distinct migration of atoms and large difference in the interfacial energy between dielectrics and Ni film. Further, it is believed that poor thermal distribution of SiO₂ also responsible for large and small size Ni islands. The Oswald ripening of smaller islands may also be responsible because larger particles are more energetically favorable than smaller islands. The island-like Ni grains significantly control the nucleation and growth of graphene. Fig. 2 shows the FESEM images of graphene layer grown on Ni surface implanted with C atoms after post rapid thermal annealing at 1000 °C. It clearly reveals graphene domains which are expected to be driven by surface property and morphology of Ni grain boundaries. Further, the graphene domains are found to be inhomogeneous because of the different nucleation sites and/or heterogeneous distribution of Ni grains. As a result, the surface diffusion of C and its segregation mechanism in Ni varies, which limits a large scale homogeneity growth of graphene.

Fig. 2 FESEM images of (a & b) C ion implantation on Ni after post rapid thermal annealing at 1000 °C, (c) direct graphene on SiO₂ after Ni film etching. The red circles demonstrate the area in which the graphene signature found, while no signature is found in the green circle area.

Raman spectroscopy, a non-destructive and well recognized technique, used to examine the number of layers and structural quality of graphene layers before and after rapid annealing. Fig. 3a shows the Raman spectra of ion implanted Ni (200 nm)/SiO₂/Si samples before and after ex situ annealing at 700 °C. We resolved the three major bands, namely D, G and 2D, which are assigned to the features of sp² bonded C–C, ensuring the formation of graphene.²⁷ These bands are found only when the laser spot strikes the top surface of the Ni grains with uniformity of maximum of 80% which is marked in red circles in Fig. 2b. No graphene features were found in between the Ni grains or the so-called voids (dark regions in Fig. 2b). The G band is due to the first order scattering of E_2g phonon at the centre of the hexagonal Brillouin zone and is a characteristic of sp²-hybridized C atoms. The 2D band originates from the two phonon double resonance excitations closed to K point in the hexagonal Brillouin zone and it is a distinctive signature of stacking dimension along the c-axis, electronic structure and strain of graphene layers. The Raman bands were not observed for the as-implanted samples. However, the G and D bands are likely to arise upon annealing at 700 °C as a result of out-diffusion and precipitation of C atoms, while the 2D band was observed with very weak intensity at 2660 cm⁻¹, possibly implying the presence of amorphous C or small structured graphene domains due to inadequate amount of C atoms out-diffused and precipitated onto the Ni surface (as depicted using eqn (2)). Further, the observed D band is due to the breathing mode of hexagonally bonded C atoms is Raman active only in the presence of defects, suggesting the subsistence of the defects in graphene lattice. However, the enhanced quality of graphene with large domains was found after annealing the samples at 1000 °C as shown in Fig. 3b. Further, we believe that even though the presence of defects could alter the shape and position of Raman 2D band, one can still estimate the layer thickness using the band. Because, the presence of defects in graphene would allow the double resonance scattering process with one being elastic and the other inelastic, leading to the signature of D band and is approximately half that of 2D band. The 2D band with a FWHM of 61 cm⁻¹ along with I(2D)/I(G) ∼ 0.7 confirm that the formed graphene is mostly bilayer. Results of these studies reveal that post annealing 700 °C may not be adequate to induce the growth of graphene with large domains and graphene fabricated at higher temperatures has better quality. This might be due to the fact that, at low temperatures, a significant of C atoms still trapped in the bulk Ni film, which restricts the number of out-diffused C atoms, thus giving rise to the formation of graphene with defective structures.^17,20,23,26

Fig. 3 Raman spectra of (a) C ion implanted on Ni samples and rapid thermal annealed at 700 °C and (b) rapid thermal annealed at 1000 °C.

To enable the direct growth of graphene on SiO₂ substrate, it is essential to remove the top graphene and Ni films using conventional etchants. This leaves only graphene sheets directly on SiO₂ substrates without any transfer process. However, the top graphene can also be utilized for application by transferring it onto other substrates using PMMA assisted wet chemical etching as one does in CVD technique. However, the goal of this technique is to fabricate and utilize the graphene directly grown on SiO₂ substrate. To remove graphene grown on top of the Ni film, the O₂ plasma treatment for 10 minutes was performed. Then, the substrate was immersed in dilute HCl or FeCl₃ solution to dissolve Ni film completely. The resultant graphene/SiO₂ was rinsed with water several times to remove residual etchant contaminants as shown in Fig. 2c. Raman spectrum was recorded to probe the features of graphene after etching Ni and is shown in Fig. 4. The 2D band at 2648 cm⁻¹ is now broadened with a FWHM of 70 cm⁻¹, implying the formation of few layered graphene structure. The enhanced D band might be ascribed to the inadequate amount of out diffused C atoms towards the SiO₂ side or the impurities formed during etching process. It is worth mentioning that, as the heterogeneous distribution of Ni grain along with C redistribution are known to drive the growth kinetics despite the amount of out diffused C is approximately equal to one monolayer density, which gives rise to the formation of bi and few layer graphene with less coverage. However, a high quality graphene without any structural defects is desirable for future nanoscale graphene electronics directly on SiO₂ substrates by this method. Large area high quality graphene may possible by optimizing the annealing procedure to control the surface out diffusion of C atoms from bulk Ni to SiO₂ side.

Fig. 4 Raman spectrum of graphene observed directly on SiO₂ substrate after etching the top graphene and Ni film.

In order to visualize the complementary structural and bonding nature, XPS spectroscopy has been performed on the annealed sample. Being a core level spectroscopy, the binding energy is sensitive to the formal oxidation state and local chemical geometry of the elements. The survey scan spectrum ensures the presence of C, Si and O peaks. The Si and O peak originate from the substrate since both the implantation and post-annealing were performed under high vacuum conditions. However, the surface oxidation during the experiments under atmospheric conditions is not ruled out. The observed XPS spectrum is deconvoluted into two peaks to distinguish the graphene from defects as shown in Fig. 5. The major peak (284.6 eV) originates from the sp² C–C bonding which offers a strong manifestation for the formation of unperturbed graphene network. The additional peak at 288.5 eV is attributed to the O=C–O bonds, which is likely to be originated from the surface oxidation.²⁰ XPS spectroscopy after etching the top Ni films reveals nearly identical features as shown in Fig. 5. Based on the results, one anticipates that being the ion implantation assisted fabrication of graphene is a kinetic controlled process, the growth of graphene on both sides of the transition metals regardless of C solubility, which offers a prospective approach to grow graphene with better controlled thickness on desired functional substrates for direct graphene electronics applications.

Fig. 5 C 1s XPS spectrum of graphene fabricated by C ion implantation.

4. Conclusions

In summary, a novel method for the direct growth of graphene on insulating substrate was demonstrated using ion implantation of C in Ni films. Graphene layers were formed on both side of the Ni surface as a result of the thermal treatment that out diffuse the C atoms from the bulk to top of the Ni and at the interface between and Ni and substrate, followed by the segregation and precipitation of C atoms. It is found that post annealing at low temperatures (700 °C and below) could lead to the graphene structures with small domains and significant disorders due to inadequate amount of out-diffused C atoms, whereas high temperature annealing lead to the formation of quality graphene with less defective. Raman and XPS spectra provided a direct evidence for the formation of graphene network on SiO₂ substrate by ion implantation. The observed morphologies and layer thickness can be modified with the ion implantation fluence and energy as well, thereby illustrating the sensitiveness and controllability of the number of layers to implanted ion fluences. A better optimization for the fabrication of large scale homogeneity of graphene by controlling thermal procedure, optimal of materials and surface out diffusion of C could improve this method as a compatible one with Si microelectronics.

Acknowledgements

K. J. thanks the Department of Science and Technology (DST), Govt. of India for the financial support to develop the infrastructural facility under the scheme of FIST and Nanomission (Contract No. SR/NM/NS-1502/2014). The authors would like to thank Prof. V. Ramakrishnan, Dr S. Balakumar, Dr V. Purushothaman, Mr P. Justin Jesuraj for their fruitful discussions.

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