Valence and electronic trap states of manganese in SrTiO₃-based colossal permittivity barrier layer capacitors

Abstract

In this study, colossal effective permittivity (ε′ ∼ 50 000) dielectrics are attained in Mn and Nb co-doped SrTiO₃-based capacitors, and the effective permittivity is explained in terms of an internal barrier layer (IBL) effect. Here, we use a combination of characterization techniques, including scanning transmission electron microscopy (STEM), electron energy loss spectroscopy (EELS), energy dispersive X-ray spectroscopy (EDS), and charge Deep Level Transition Spectroscopy (Q-DLTS) to confirm the presence of interfacial electronic traps in an air co-fired capacitor with Pt internal electrodes. The IBL was developed by an oxidative annealing process, leading to improved dielectric loss and breakdown voltages. The elemental mapping confirms that the dopant has a Mn-rich segregation layer in the grain boundaries and also at the electrode/ceramic interface. The EELS results reveal the valence change of manganese changed from a mixed Mn²⁺/Mn³⁺ to a mixed Mn³⁺/Mn⁴⁺ during an annealing process. The valence changes helps to enhance the Schottky barrier height at the grain boundaries, and this is quantified by a Capacitance–Voltage (C–V) analysis. Moreover, Q-DLTS results are presented to show the three electronic traps existing at IBL. All these changes with oxidative annealing are also discussed and related to the electrical and dielectric property trends.

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Introduction

It is of interest to search for colossal permittivity (CP, ε′ > 10⁴) materials with low dielectric loss for microelectronics applications.^1,2 Recently, CP materials have been reported in several material systems such as doped-BaTiO₃,³ CaCu₃Ti₄O₁₂,^4,5 doped-NiO,⁶ CuO,⁷ La_2−xSr_xNiO₄,⁸ and doped-TiO₂.^9–11 Strontium titanate (SrTiO₃)-based ceramics are still one of the most widely used materials for grain boundary barrier layer capacitors because of low dielectric loss, temperature stability with large dielectric constant.^12–17 Such novel properties are explained in terms of the back-to-back Schottky barriers at the grain boundaries resulting from interfacial electronic traps with n-type grains. It has been proposed that the nature of the traps could be related to cation vacancies,^18,19 or chemisorbed oxygen.^20–22 Also a segregated acceptor solute, such as Cu, Fe or Mn, is known to have an additional influence on the interfacial state.^18,23,24 In fact, the Mn additive is often used to improve a variety of the properties in the electroceramics, such as PTCR thermistor,^25,26 capacitors,²⁶ and varistors.^27–29 Although a comprehensive understanding has not been reported to date, Mn is thought to be particularly effective because it forms an additional deeper trap state^18,30 or it affects the oxidation rate at the grain boundaries by changing its valence state.^22,31 Therefore it would be important for the development of ceramics capacitors to understand the role of the dopant Mn and the oxidative heat treatment, and how they affect microstructure and electronic structure change.

In the present study, we systematically consider the effect of the oxidative annealing and characterize the valence states of Mn on the macroscopic dielectric properties. First, Mn and Nb co-doped SrTiO₃ single layer capacitors with Pt internal electrodes were prepared by sintering under a reducing condition and underwent a subsequent oxidative annealing with varying times. Our sintering condition produces lower valence states of Mn, and then an oxidative annealing introduces higher valence states.³² Detailed studies of microstructure, local valence states, and interfacial electronic states were performed. The structure – property – processing relations give insights into the development of high performance barrier layer capacitors or colossal permittivity dielectrics.

Experimental

Sample preparation

The specimens were prototyped by a conventional mixed oxide process.³³ The starting materials used in this study were reagent-grade SrCO₃ and TiO₂ (99% and 99.99% purity, respectively; Alfa Aesar). The starting materials were dried at 120 °C for 24 h to remove absorbed water. These dried powders were then accurately weighed to a stoichiometric composition of SrTiO₃ and mixed with 0.6 mol% Nb₂O₅, 1 mol% TiO₂, 1.0 mol% MnO₂, and 10 wt% ZnO–B₂O₃ flux with zirconia milling media and ethanol by ball milling for 24 h. The powders were deflocculated and were prepared in a two-step typical tape fabricating procedure. First, the mixture was ball milled with vehicle A (5 wt% polyvinyl butyral and 95 wt% MEK/ETOH organic solvents) for 24 hours to well disperse powder in vehicle to become slurry. Second, the slurry was ball milled with vehicle B (22 wt% polyvinyl butyral, 10 wt% plasticizer and 68 wt% MEK/ETOH organic solvents) for 24 h. The resultant so-called slip was then tape-casted to a green sheet of 35 μm in thickness using doctor-blade method. Platinum paste was screen printed as the internal electrode onto green sheets, using 350 mesh stainless steel screen. Printed sheets were then stacked and pressed at 55 °C in a square mold, successively using isostatic laminators. The green chips were cut to the size corresponding to 5 mm × 3.5 mm final chip size which contains one active layer. After debinding at 550 °C for 8 h, the green chips were sintered at 1400 °C for 5 hours in the in a 5% H₂/95% N₂ forming gas (pO₂ ∼ 10⁻¹³ atm). The as-sintered samples underwent reoxidation in a cube furnace at 1200 °C for 50 minutes to 10 hours at a heating and cooling rate of 3 °C min⁻¹ in air. In addition, (1.0 mol% Mn)-doped SrTiO₃ and (0.6 mol% Nb)-doped SrTiO₃, without adding Nb₂O₅ and MnO₂, were also prepared under the same conditions, respectively. Disk-shaped samples without inner electrodes were also prepared for X-ray diffraction measurement. The powder was prepared by the same process described above and then pressed into disk-shaped pellet without any binders. The pellets were further pressed using cold isostatic pressing. The disk-shaped samples were reoxidized in air for 60 and 600 min after the sintering process.

Electrical and dielectric characterization

Capacitance of the samples was measured over a frequency range of 100 Hz to 1 MHz using a computer-controlled LCR meter (HP4284A, Hewlett-Packard, USA) at room temperature. The d.c. current–voltage characteristics were measured at room temperature with a pA meter (HP 4140B, Hewlett Packard, USA). The current was measured after applying the d.c. bias for 1 (min). Q-DLTS characterization was performed in a home-made charge measurement system.³⁴ Partially doped samples were used in addition to (Mn, Nb) doped-SrTiO₃ in order to investigate the nature of trap. In this study, 100 μs duration of pulse voltage was applied with 1 V of magnitude.

Microstructure characterization

X-ray diffractometer (XRD) (PANalytical Empyrean) with CuKα₁ radiation (λ = 1.5406 Å) was utilized to identify the crystal structure. The sintered surface of the samples was first polished and then scanned at 0.02° intervals of 2θ in the range of 10–70°. Microstructural and chemical studies were performed on both segregation layer and grain region using a TITAN (FEI, TITAN G2 60–300 kV) microscopy equipped with an Electron Energy Loss Spectrum (EELS) system operating at an accelerating voltage of 200 kV. The samples annealed for 60 and 600 (min) were chosen to understand the change during the annealing. Cross section specimens for transmission electron microscopy (TEM) were prepared via standard procedures, including mechanical thinning, polishing, and ion milling. The specimens were polished down to 20 μm, and then mounted on molybdenum grids. The foils were further thinned with an Ar-ion mill (Gatan, PIPS II) until an electron transparent perforation was formed. A cryogenic stage was used to cool the specimen to the liquid N₂ temperature during ion milling to minimize structural damage and artifacts. Microstructural and chemical studies were performed on a TITAN (FEI, TITAN G2 60–300 kV) microscopy equipped with an Energy Dispersive X-ray Spectroscopy (EDS) system and an Electron Energy Loss Spectrum (EELS) system operating at an accelerating voltage of 200 kV. The EDS mapping and EELS measurements were achieved under scanning transmission electron microscopy (STEM) mode. Monochromator was used to ensure the energy resolution of EELS experiments, and the half-maximum height of the zero-loss peak was 0.175 eV. The relative sample thickness, as estimated from t/λ of the zero-loss spectrum, was between 0.3–0.5 (λ is the inelastic scattering mean free path). To accurately monitor the random fluctuations of the signal along the energy loss scale, zero-loss peak was also simultaneously recorded by employing the attached dual-EELS instrument, and then the drifting of the obtained white lines was corrected.

Results and discussion

Fig. 1 shows XRD pattern of the disc-shaped (1% Mn + 0.6% Nb)-doped SrTiO₃ capacitors annealed for 60 and 600 min. A cubic symmetry of SrTiO₃ is detected in the both specimens and any secondary phase was not observed.

Fig. 1 Measured XRD data for disc-shaped (1% Mn + 0.6% Nb)-doped SrTiO₃ capacitors annealed for 60 min, and 600 min.

Fig. 2 shows frequency dependence of dielectric properties of the (1% Mn + 0.6% Nb)-doped SrTiO₃ capacitor with different annealing time. Colossal effective permittivity (ε′ > 10⁴) was obtained in all the samples. The values were almost invariant to frequency (from 100 Hz to 1 MHz) and decreased with the increase in the annealing time. This would be consistent with the barrier layer width increasing by the annealing, and thus barrier layer capacitance was thereby decreased. The same trend in the dielectric loss (tan δ) at the low frequency regime also indicates the thicker barrier layers, which leads to higher grain boundary resistance. The minimum value of tan δ is found to be ∼0.008 at ∼8 kHz in the 600 (min) annealed samples while tan δ < 0.03 was maintained in the range from 500 to 3.5 × 10⁵ Hz. These dielectric properties are superior or/and comparative to existing IBLCs.^5–7 It is also noted these can be further improved by modifying the oxidative annealing conditions.

Fig. 2 Dielectric properties in terms of a relative permittivity in (1% Mn + 0.6% Nb)-doped SrTiO₃ capacitors with different annealing time: (□) 50, (△) 100, (○) 200 and (▽) 600 (min).

Fig. 3 shows the result of current density–electric filed (J–E) characteristics of (1.0% Mn + 0.6% Nb)-doped SrTiO₃ capacitors annealed for different times. The non-linear characteristics were clearly observed in all the samples, suggesting that IBLC effect plays important role in these specimens.^27,35,36 Both insulation resistance and breakdown voltage (V_B at J ∼ 1 mA cm⁻²) improve with the increase of the annealing time. This could be also explained in terms of the change in the barrier layer width. Detail discussion is made in the later section.

Fig. 3 Current density–electric filed (J–E) characteristics of (1.0% Mn + 0.6% Nb)-doped SrTiO₃ capacitors annealed for different times: (□) 50, (△) 100, (○) 200 and (▽) 600 (min).

Fig. 4a and b show the elemental mapping near the grain boundary in the samples annealed for 60 and 600 (min). It reveals a Mn and Nb rich phase at the grain boundary in the 60 (min) annealed samples, as shown in the Fig. 4a. Such a phase was barely observed at the grain boundary after annealing for 600 (min), though a small amount of Mn still remained (Fig. 4b). Thus, 600 (min) of oxidative annealing would be long enough for dopants to diffuse into the grains.

Fig. 4 Elemental mapping at the grain boundary region for the sample annealed for 60 (min) (a) and 600 (min) (b), and at the interface with electrode for the sample annealed for 60 (min) (c),and 600 (min) (d).

Fig. 4c and d show the elemental mapping near the electrode/ceramic interface in the samples annealed for 60 and 600 (min). The Mn was heavily segregated from the grain region and formed Mn-rich layer near the electrode/ceramic interface. Meanwhile, Sr is found to be depleted from electrode/ceramic interface while both Ti and O still remained. Minor differences in the microstructure between 60 (min) and 600 (min) annealing samples near the electrode/ceramic interface are found.

Fig. 5 shows an EELS spectra of O-K, Ti-L_2,3, and Mn-L_2,3 edges in the samples annealed for 60 (min) and 600 (min) at the electrode/ceramic segregation area and at the grain region. The Mn-L₃ edge in the Fig. 5a and d exhibits a double peak, which can be interpreted as mixed valence states.³⁷ The peaks locate at ∼642.5 (eV) and ∼643.9 (eV) for the 60 (min) annealed sample and at ∼644.5 (eV) and ∼645.8 (eV) for the 600 (min) annealed sample. Rask et al.,³⁸ reported that the position of Mn-L₃ edge is at 642.44 (eV) for Mn²⁺, 643.82 (eV) for Mn³⁺ and 646.45 (eV) for Mn⁴⁺. Therefore, it is likely that the two peaks in the 50 (min) annealed sample correspond to Mn²⁺ and Mn³⁺, respectively. For the sample annealed for 600 (min), the peak corresponding to Mn²⁺ disappears, while the Mn⁴⁺ state is observed. This may be due to the initial sintering condition producing a Mn²⁺ state, and it still remained even after annealing for 60 (min).

Fig. 5 EELS spectra of Mn-L_2,3 edge, Ti-L_2,3 edge and O-K edge for the (1.0% Mn + 0.6% Nb)-doped SrTiO₃ capacitors with 60 (min) ((a)–(c)) and 600 (min) ((d)–(f)) annealing times. EELS was performed on the segregation layer (Seg) and the grain region (STO). Mn-L_2,3 edge was obtained only from the segregated layer.

In Fig. 5b and e, both Ti-L₂ and L₃ edge show clear peak splitting. The number of peaks and their shape depend on valence state, coordination, and site symmetry of the Ti cations.³⁹ The peak position, on the energy axis is highly related to local nonstoichiometry, in which oxygen deficiency leads to lower energy loss position.⁴⁰ The measured Ti-L_2,3 spectra from both segregation layer and grain region are shifted to higher position with increasing annealing time. It is clearly consistent with the Ti⁴⁺ ion being generated by annealing, which also annihilates oxygen vacancies.

Fig. 5c and f shows O-K edge at the segregation and grain region. In the grain region, the intensity of O-K edge increased with the increase in the annealing time. It has been reported⁴⁰ that higher oxygen vacancy would lead to weaker O-K edge intensity. The peak shape of O-K edge from the grain region is very similar to the reported result.⁴⁰ Interestingly, the O-K edge from the segregation layer in the Fig. 5c and f is quite different from the one from the grain region. This remarkable difference can be seen at ∼540 (eV) in Fig. 5f. The absence of one peak has been reported in Ti_xO_y system.^39,41 Thus, the difference of O-K edge could be explained if a non-perovskite structure of the segregation layer is assumed. The Ti_xO_y phase can be commonly found in the SrTiO₃ system,^42,43 and the elemental mapping also confirmed the absence of Sr in these Mn-rich segregated regions (Fig. 4). This secondary phase was not observed by the XRD measurement because Ti_xO_y phase exist near the electrode so that it should be caused by the co-firing with inner electrodes.

A C–V analysis was carried out to characterize the potential barrier at the grain boundary. For the double Schottky barriers at the grain boundaries, the bias dependence of capacitance can be expressed as:⁴⁴

where C is the capacitance per unit area, q is the electronic charge, ε is the permittivity of the grain, N_d is the donor concentration in the grain, ϕ is the Schottky barrier height, and C₀ is the capacitance per unit area without the bias voltage. The density of surface states (N_s) and depletion layer width (L) can be estimated by:

N_s = N_dL (3)

(1/C − 1/C₀)² plot is shown in the Fig. 6. The parameters in the Table 1 are calculated from the slope and intercept of the data shown in Fig. 6. The values are comparable to reported values in the SrTiO₃-based varistor.^27,45 It was found that ϕ and L continuously increased with increased annealing time, which can be associated with the decrease in N_d, based on eqn (2) and (3). The oxygen vacancies are known to act as donor in the semiconductor. As discussed above, the EELS showed that the oxygen vacancy concentration decreased with the increase in the annealing time, while the Mn valence state increased. Thus, oxidative annealing was effective in that it increased ϕ and L by decreasing N_d. It is also possible that Mn promoted oxidation at the grain boundaries by changing its valence state.³¹ Overall, the increase of the barrier height is consistent with the change of the breakdown voltage with increasing the annealing time (Fig. 3). The increase in L with increased annealing time could lead to the decreased effective permittivity (Fig. 2). The macroscopic dielectric and electrical properties is explained in terms of modification of internal barrier properties (ϕ and L).

Fig. 6 C–V measurements of (1.0% Mn + 0.6% Nb)-doped SrTiO₃ capacitors with different annealing time: (□) 50, (△) 100, (○) 200 and (▽) 600 (min). Less voltage was applied on the 50 (min) annealing sample because the breakdown was expected above V_g = 1 (V).

Table 1 Summary of C–V and Q-DLTS result

Annealing time (min)	ΔET1 [eV]	ΔET2 [eV]	ΔET3 [eV]	Nd [cm^−3]	ϕb [eV]	Ns [cm^−2]	L [nm]
a ΔET3 of the sample annealed for 50 min was not obtained due to its weak signal.
50	0.50	0.56	—^a	7.6 × 10^19	2.1	2.3 × 10^14	30
100	0.47	0.54	0.64	5.2 × 10^19	2.2	1.9 × 10^14	37
200	0.49	0.53	0.73	4.1 × 10^19	3.3	2.1 × 10^14	51
600	0.48	0.58	0.76	3.1 × 10^19	4.6	2.2 × 10^14	69

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Finally, Q-DLTS was performed in order to investigate the trap states at the interface. DLTS signal is defined as the charge released during the time interval from t₁ to t₂.

where Q₀ is a constant and τ is the time constant. When ΔQ = ΔQ_max, τ is simply given by

τ_m = (t₂ − t₁)/ln(t₂/t₁) (5)

Under these conditions, the trap level ΔE_T can be described in terms of τ_m and temperature T as follows:^46,47

where Γ is a material constant. Fig. 7 shows the DLTS signal of the samples annealed for 50, 100, 200, and 600 min. Three DLTS peaks were found at ∼160, 230 and 350 K, respectively, indicating multiple trap states. The trap states, which is essential for the formation of back-to-back Schottky barriers,⁴⁸ are successfully detected. The values of each of the trap levels were obtained from an Arrhenius plot using eqn (6) and are shown in Table 1. The trap levels corresponding to the first and second peak were found to be insensitive to the annealing time, while the third trap formed at deeper level as annealing time increased. To further investigate the nature of trap, DLTS was applied to partially doped SrTiO₃ capacitors. Fig. 8 shows the DLTS signal of (0.6 mol% Nb)-SrTiO₃ and (1.0 mol% Mn)-SrTiO₃ capacitors annealed for 50 (min). Though signals were weak, all three peaks in (1.0 mol% Mn)-doped SrTiO₃ were observed almost at the same peak position in (1.0 mol% Mn + 0.6% Nb)-doped SrTiO₃, as shown in Fig. 7 and 8a. However, the third peak, which was found at ∼350 K in both (Mn, Nb)-doped and Mn-doped-SrTiO₃, was clearly suppressed in (0.6 mol% Nb)-SrTiO₃ as shown in Fig. 8b. Therefore, the third peak is then deduced to be attributed to Mn-doping. Based on the EELS result, the deeper trap state might be owing to the change of valence state of Mn and hence contributed to the increase of barrier height. Moreover, the first and second peak were observed in all samples despite the dopant difference. These trap states should be created by an intrinsic defect, such as cation vacancies or chemisorbed oxygen, as mentioned in the previous section.

Fig. 7 DLTS signal of (1.0% Mn + 0.6% Nb)-doped SrTiO₃ capacitors with different annealing times. The gate time was set to t₁/t₂ = 48 μs/480 μs.

Fig. 8 DLTS signal of (1.0% Mn)-doped SrTiO₃ (a), and (0.6% Nb)-doped SrTiO₃ capacitor (b) with t₁/t₂ = 48 μs/480 μs. The symbols are the experimental data and the solid lines are the fitting curves. The insets show the lower temperature region with higher magnitude.

Conclusions

In summary, we report on the correlations between microstructure, chemical valence state, and electrical properties with increasing oxidative annealing time in the SrTiO₃-based barrier layer capacitor, which possessed very high 10⁴ effective permittivity. Elemental mapping confirmed Mn was heavily segregated to electrode/ceramics interfaces. EELS analysis revealed that the ratio of mixed valence state of Mn with the increase in the annealing time, while oxygen was incorporated into grains. During these change, all of the Schottky barrier height at the grain boundaries, depletion width, and trap level of Mn were increased. These results correlate with the changes in the dielectric and electric properties with increasing annealing time and can be used to guide optimization of colossal permittivity or barrier layer dielectric design.

Acknowledgements

This work is supported by the National Science Foundation, as part of the Center for Dielectrics and Piezoelectrics under Grant No. IIP-1361571 and 1361503. Authors are grateful to Materials Characterization Lab staff at The Pennsylvania State University, and Mr Okamoto at Murata Manufacturing Co., Ltd. for their helpful discussions. K. Tsuji would like to thank ITO Foundation for International Education Exchange for the financial support. W. T. Chen would like to thank MOST 104-2622-E-006-038-CC3 Ministry of Science and Technology R.O.C. for the financial support.

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