Silicon nanowires and nanotrees: elaboration and optimization of new 3D architectures for high performance on-chip supercapacitors

Abstract

Micro-supercapacitors are increasingly foreseen as future energy storage or power buffer solutions for small scale integration on-chip. However, widely used electrode materials or electrolytes often proved to be incompatible with microelectronics processes. Although being the material of choice for on-chip integration, nanostructured silicon electrodes only recently caught attention for potential applications, and they displayed promising results especially for bottom-up silicon nanostructures, where the design liberty and fine control of nanostructure morphologies allow considerable improvements. The present work deals with the optimization of highly doped silicon nanowires (Si-NWs) and nanotrees (Si-NTrs) pioneered in the laboratory using an innovative, fast and efficient electroless gold deposition method in order to explore a wide variety of 3D architectures and their physicochemical properties. Through a systematic study of branches and trunks morphologies, the nature inspired nanotrees have been drastically improved compared to previously published works, resulting in excellent electrode properties, showing high energy and power densities, respectively, up to 2.8 mJ cm⁻² and 235 mW cm⁻². In addition, a cyclability of over a million charge–discharge galvanostatic cycles was determined using an enlarged electrochemical window of 4 V in an ionic liquid electrolyte.

---

Introduction

For the last 30 years, tremendous new applications have become reality with the development of portable electronics. However, whereas electronic components drastically reduced in size, shape and power consumption thanks to the improvements of the silicon industry, batteries limited the design of the new devices due to their large size and the always growing need for power and energy of the applications. Moreover, reducing the size of batteries to the micro-scale remains an extremely challenging problem that hinders potential breakthroughs in the field of micro-electronic devices, such as implantable medical devices, active RFID or wireless sensor networks (so called “smart dust”).

In order to fulfill the requirements of such devices, micro-supercapacitors have recently attracted substantial attention^1,2 owing to their high power and energy densities, their excellent cycling ability compared to batteries and the relatively simple scalability of the processes at extremely small scale (down to less than a square millimeter of geometric surface area).³ Among all materials, carbon⁴ stands in high grounds for pure double layer electrochemical capacitors, due to its simplicity of use, relative abundance and ease to achieve high specific capacitance. Several carbon based electrode materials display promising results for micro-supercapacitors applications, such as “onion like carbon”,^3,5 activated carbon,^3,6–8 carbon nanotubes,^9,10 graphene materials,^10–13 or carbide derived carbons.¹⁴ Pseudocapacitive compounds,¹⁵ for instance metal oxides (RuO₂,^16,17 MnO₂…^18–20) and nitrides (TiN,²¹ VN^22,23) or conductive polymers (PEDOT and derivatives,^24,25 PPy,²⁶ PANi…²⁷) have also been intensively investigated owing to their extremely large specific capacitance due to fast and reversible surface redox reactions.

However, most of the materials studied in the literature still present some inherent incompatibilities for integration on a regular electronic device. For example the high temperature solder reflow conditions used to attach devices on an electronic circuit (usually over 200 °C for several tens of seconds) would be problematic for most aqueous electrolytes used for pseudocapacitive oxide materials, or fragile carbonaceous materials. Advanced new materials thus need to be designed directly from the on-chip integration point of view.

Although ubiquitous in micro-electronics for decades, silicon only recently attracted attention as a potential material for “on chip” micro-supercapacitor integration. Despite having excellent thermal stability, evident “on chip” applicability and tunable electrical properties, only a handful of studies were conducted on this field. The main drawback of silicon consists in the extreme difficulty to tailor large surface area conductive silicon, since highly porous silicon remains extremely fragile and reactive. While achieving fairly stable large surface area conductive carbon leads to specific capacitances over 100 F g⁻¹ with a good cycling stability, designing conductive porous silicon nanostructures with a sufficient surface area to exhibit interesting capacitances but also keep a good stability still represents a challenge. In addition, on-chip applications are rather limited in terms of geometric area occupied by the device, than by mass or volume of active material, thus the studied compounds should be compared by surface specific capacitances in F cm⁻². This parameter explains why certain materials can be advantageous for micro-supercapacitor devices albeit delivering poor mass-specific capacitances.

In this context, two main methods can be employed in order to yield conductive 3D nanostructured silicon electrodes for supercapacitors: the top-down approach²⁸ consisting principally in etching a conductive silicon substrate to yield porous silicon or etched Si-NWs and the bottom-up approach usually via Chemical Vapor Deposition (CVD) resulting in silicon nanostructures grown on a substrate (e.g. Si-NWs, Si-NTrs).

Top-down etching although simple and relatively inexpensive yields high surface area silicon nanostructures,²⁹ that can be used in supercapacitors. Nonetheless, the fragility and lack of control on the electrical properties of the nanostructures often require a conformal coating in order to upgrade capacitance and cyclability, for instance with carbon,³⁰ graphene,³¹ diamond,³² titanium nitride³³ or silicon carbide³⁴ with capacitance values up to 325 mF cm⁻² for carbon sheath coated porous Si-NWs.³⁵

On the other hand, bottom-up silicon nanostructures can be finely tuned in terms of morphology and electronic properties,³⁶ with moderate to high surface enhancements compared to bulk silicon at the expense of a complex and pricy material synthesis process. Moreover, bottom-up approach permits a remarkable liberty in the design of innovative nanostructures, such as silicon-nanotrees, where the addition of branches to Si-NWs allows obtaining high surface area yet robust and conductive supported electrode materials. After the original work by Thissandier et al. on CVD Si-NWs as electrodes for supercapacitors,³⁷ highly doped Si-NWs and Si-NTrs displayed unmatched characteristics using ionic liquid electrolytes (EMIM TFSI, PYR₁₃ TFSI), with a 4 V electrochemical window,^38,39 up to 225 mW cm⁻² power densities, and more than 10⁶ charge/discharge cycles without significant damages.⁴⁰ Contrary to most top-down Si-nanostructures, these properties are obtained for uncoated pure Si-nanostructures, compatible with microelectronics fabrication processes and with capacitances up to 900 μF cm⁻² in three electrodes cell setup reported for Si-NTrs.⁴⁰

However, capacitance still needs to be further increased to reach interesting values for on chip integration.

In particular, CVD catalyst optimization has scarcely been explored in the literature, although it remains one of the simplest paths to change and improve the bottom-up nanostructures morphologies. Bottom-up silicon nanostructures are most frequently synthetized using colloid³⁷ or thin film evaporation⁴⁰ to deposit the gold catalyst. However, these techniques are expensive and non-selective, for instance gold evaporation require a high vacuum and usually deposits gold over the whole deposition chamber, thus consuming large quantities of precious metal. The non-selectivity can hinder on-chip applications, for instance if gold is unselectively deposited on microfabricated on-chip Si-NWs electrodes to produce Si-NTrs, it would require delicate patterning steps to remove the excess gold before the second CVD step. For these reasons this study uses an innovative, selective and time efficient electroless gold deposition method,^41,42 for the first time in the field of bottom-up silicon supercapacitors to the best of our knowledge.

The aim of the present work is to design and optimize silicon nanowires and nanotrees using electroless gold deposition in order to explore the variety of morphologies and properties made possible by the bottom-up approach and to maximize the specific capacitance of such system. Among the endless possibilities offered by the CVD growth, this study will mainly focus on a two steps synthesis of Si-NTrs, with the aim of optimizing synergistically trunks and branches diameter, densities and lengths to increase the capacitive properties of the electrodes.

Experimental section

Si-NWs synthesis

Highly n doped 100 mm 〈111〉 silicon wafers (<5 mΩ cm, As doped, Silicon Materials Inc.) were diced into 1 × 1 cm² squares and thoroughly rinsed in acetone and isopropanol. Any organic traces were then removed by dipping the samples in piranha solution (H₂SO₄ 96% + H₂O₂ 30% 3 : 1) for 1 minute, followed by native silicon oxide removal by 10% HF for 1 minute. Gold deposition was performed by drop casting the electroless plating gold solution on the sample for 15 s, then the samples were vigorously rinsed in DI water and dried by blowing nitrogen. These gold plating bath with various AuCl₄⁻ concentrations were freshly prepared before each deposition by mixing 10% HF with a gold stock solution (20 mM AuCl₄⁻, 1 M HCl in DI water) in order to achieve the desired AuCl₄⁻ concentrations in 2.5 M HF aqueous solution. The samples were then rapidly transferred to the CVD quartz tube hot wall reactor for the Si-NWs growth. The nanostructure growth is carried at 650 °C under 6 Torr total pressure, 700 sccm of H₂ carrier gas, 40 sccm of SiH₄ precursor gas, 90 sccm of doping gas (0.2% PH₃ in H₂) and 100 sccm of HCl. The growth rate under these conditions is about 2.5 μm min⁻¹ and the yielded 50 μm long Si-NWs are highly conductive.³⁶

Si-NTrs synthesis

The three types of Si-NWs obtained in the previous section were used as trunks samples for the Si-NTrs generation. These trunks were first immersed in a gold etching solution (KI/I₂ in DI water) for 15 seconds in order to remove the gold droplets on top of the nanowires and thoroughly rinsed in DI water, then the electroless gold plating solution was directly applied on the Si-NWs samples for 15 seconds with the same procedure than for the Si-NWs, and the obtained gold plated Si-NWs were rapidly transferred in the CVD reactor for the second growth. The branches growth is performed at 600 °C under 6 Torr total pressure, 500 sccm of H₂ carrier gas, 50 sccm of SiH₄ precursor gas, 100 sccm of doping gas (0.2% PH₃ in H₂) and 100 sccm of HCl. The lengths of the branches are controlled by varying the growth time.

Electrodes characterizations

Nanostructures morphologies are studied by scanning electron microscopy (Zeiss Ultra 55) with 10 kV accelerating tension, with 0, 45 and 90° inclinations. For 90° pictures, the samples were previously cleaved in order to study a clean sample cut. The images were then analyzed using ImageJ (Rasband, W.S., ImageJ, U. S. National Institutes of Health, Bethesda, Maryland, USA, http://imagej.nih.gov/ij/, 1997–2014). The diameter distribution estimations of trunks or branches were measured using at least 3 different SEM micrographs with 100 unique manual measurements on each picture. The density of the Si-NWs was roughly evaluated by counting the Si-NWs and by using the “Find Maxima” function of ImageJ with a careful choice of the noise tolerance to pick the Si-NWs tips only. Since the Si-NWs density evaluation is performed from top view SEM micrographs, this evaluation only takes into account the Si-NWs visible on top of the Si-NWs forest thus is only a rough estimation.

All electrochemical characterizations were performed in an argon filled glove box at room temperature in order to avoid any water or oxygen contamination. The electrolyte used in all measurement was 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide (EMI-TFSI) ionic liquid purchased from Solvionic (France) with 99.5% purity (≤0.05% water and ≤0.001 ppm of halide content) and used without further purification.

Gold mass estimations were conducted by weighing several 1 cm² samples at the same time on a Mettler Toledo AG245 balance with 0.01 mg readability, and by considering eqn (1) to calculate the quantity of gold deposited from the samples mass difference:

3Si + 18HF + 4AuCl₄⁻ → 3SiF₆²⁻ + 4Au + 18H⁺ + 16Cl⁻ (1)

The total mass of the optimized Si-NTrs grown on the sample was also calculated by the same scaling method, with a total mass of Si-NTrs approximating 1.2 μg cm⁻² ± 0.2 μg cm⁻².

Three electrodes cell measurements were conducted using a homemade Teflon cell connected to an Autolab PGSTAT302 potentiostat/galvanostat equipped with a FRA 2 module. The nanostructured electrode (active area 0.4 cm²) was used as the working electrode with a twisted platinum wire as the counter electrode and an Ag/Ag⁺ reference electrode (10 mM silver trifluoromethanesulfonate in EMI-TFSI). Each electrode was tested by cyclic voltammetry at different scan rates (between 50 mV s⁻¹ and 10 V s⁻¹) with a 4 V electrochemical windows. Impedance spectroscopy was also measured by applying 10 mV amplitude signals from 0.01 to 100 000 Hz. The capacitance values from CV curves were measured after a few hundred CV cycles at 1 V s⁻¹ to avoid any parasitic effects of surface oxide formation or ionic liquid impurities reactions.

Two electrodes cell measurements were performed by sandwiching a glass fiber paper separator soaked in EMI-TFSI between two symmetric nanostructured electrodes connected to a potentiostat/galvanostat (VMP3, Bio-logic, France). EIS (50 mV amplitude signal, 0.01 to 400 000 Hz), cyclic voltammetry at different scan rates and galvanostatic charge/discharge cycling at different current densities were conducted. Areal capacitance values were calculated from CV and galvanostatic charge/discharge curves using respectively eqn (2) and (3):

where Δi is the current difference measured at the center of the electrochemical window, S the electrode surface, v the scan rate, U_max the electrochemical window, and Δt the discharge time. Unless otherwise stated, all capacitance values given in this paper are derived from capacitive currents measured from cyclic voltammetry curves at 1 V s⁻¹ at the center of the electrochemical window. Equivalent Series Resistance (ESR) was estimated from the real part of the impedance at maximum frequency in EIS measurements. Maximum power density P_max was derived from eqn (4) and energy density E and power density P respectively from eqn (5) and (6):

Results and discussion

Si-NWs and Si-NTrs electrodes synthesis method

Fig. 1 illustrates the process used for the Si-NWs and Si-NTrs growth. First, a gold catalyst layer is deposited on clean, deoxidized and highly conductive silicon wafer squares. The samples then undergo CVD growth via the VLS (Vapor Liquid Solid)⁴³ process, yielding Si-NWs with desired electrical and structural properties. Briefly, the mechanism for this growth starts with the dewetting of the gold layer on silicon upon annealing, which leads to droplets of Au–Si eutectic scattered on the sample surface. These droplets will catalyze the cracking of a silicon precursor gas (SiH₄) and induce the growth of a single crystalline nanowire under the catalyst droplet in epitaxy with the substrate. Fig. S1† displays HR-STEM pictures of 2 mM Si-NWs confirming the single-crystallinity of the nanowires. The electrical conductivity of the nanostructures can be precisely controlled by adding a doping gas, and HCl gas can be added to avoid any undesired tapering of the nanowires and improve the doping quality.⁴⁴ By varying the growth conditions and the amount of gold deposited on the samples, the length, mean diameter and density of the nanowires can be finely tuned for the desired applications.

Fig. 1 (a) Fabrication steps for the design of silicon nanotrees electrodes (b–e) SEM micrographs of the nanostructure growth steps: (b) gold layer on a silicon wafer, (c) 50 μm long silicon nanowires after 1^st CVD (d) gold coated Si-NWs, (e) Si-NTrs subsequently obtained after 2^nd CVD growth with 20 μm long branches (inset showing a higher magnification of the nanostructure).

After this step, the obtained Si-NWs or trunks can be coated with a layer of gold catalyst and another CVD growth will lead to branches on the trunks, yielding a sample covered by a highly conductive silicon nanotrees forest.

The main interest of this nanostructuration is to obtain a large enhancement of the specific surface, which will lead to an increase in the capacitance of the electrode. In order to achieve the largest value of specific surface, the nanotrees should be optimized in regard to the densities, lengths and diameters of both trunks and branches.

This study also displays the fact that some parameters are interdependent, such as the density and the mean diameter of the Si-NWs, or the trunks diameters and the branches densities. For instance, increasing the diameter of the trunks can decrease their density, and thus reduce the overall specific surface of the Si-NWs electrode. However, large diameter trunks can also achieve higher branches densities, which can be in total more profitable than using higher density but lower diameter trunks.

In order to determine the best nanostructure morphology for supercapacitor applications, this study focuses on two main parameters highlighted in Fig. 1:

- The gold catalyst quantities which will affect both mean diameter and density of the Si-NWs or Si-NTrs’ branches. This step has been performed by using electroless gold deposition method.⁴⁵

- The length of the trunks and branches which are solely depending on the CVD growth time with other parameters being kept similar.

All other parameters were kept similar during the production of the samples. Using this simple method, a systematic experimental study was conducted on several points: trunks diameters and density, branches diameters and densities on different trunks samples and finally branches lengths comprised between 5 and 70 μm. Nanostructured electrodes were designed by varying these parameters and were both studied in three and two electrodes cells configurations, using EMI-TFSI as the electrolyte as previously reported.³⁸

Electroless gold deposition method

The CVD catalyst deposition step uses a spontaneous galvanic displacement reaction occurring between silicon immersed in hydrofluoric acid, and metal ions in solution. Silicon is oxidized according to eqn (7), providing electrons to reduce the gold ions as shown in eqn (8).⁴²

This reaction can be extremely quick, thus reducing sample preparation time and is performed in water, at room temperature, with only a fraction of a milliliter of dilute AuCl₄⁻ solution consumed per sample. Moreover, the gold plating occurs only on silicon surfaces, facilitating patterning and on-chip integration of Si-NTrs. The gold quantity deposited can also be easily tailored by varying the plating bath concentration or deposition time, and yields relatively conformal gold layers even on complex geometries.

Consequently, the Si-NTrs synthesized in this study were grown using two electroless deposition steps with various concentrations to optimize the parameters described in the previous section. Three different concentrations of AuCl₄⁻ were used for these two steps, 10 mM, 2 mM and 1 mM respectively. The nanostructures yielded will be referred by the concentration used for each electroless steps, for instance 10 mM trunks will correspond to Si-NWs obtained by CVD of a sample coated by 10 mM electroless bath, and 2 mM/10 mM Si-NTrs will correspond to silicon nanotrees yielded by CVD of 2 mM trunks coated by 10 mM for branches.

Influence of the trunks diameters and densities

Fig. 2(a–c) picture the differences in the gold quantities deposited on the Si bulk substrates using these three different conditions. At high concentrations, a semi-covering layer of gold is formed on the surface of the silicon, whereas at lower concentrations, only small nanoparticles are deposited on the surface. This is directly related to the kinetics of the electroless deposition reaction, where a low concentration permits only the rapid seeding of gold nanoparticles, whereas higher concentration allows the seeding, growth and Ostwald ripening of the nanoparticles leading to a quasi-covering film in the same amount of time. A rough estimation of the gold masses deposited on the samples is provided in ESI.† These samples were used to conduct CVD growth, leading to extremely different Si-NWs morphologies (Fig. 2(d–f)). First, the diameters distributions of the samples shifted from relatively large diameters to smaller values by decreasing the gold precursor concentration, with mean diameters respectively being 180 nm ± 100 nm, 61 nm ± 26 nm and 44 nm ± 18 nm for 10, 2 and 1 mM concentrations (Fig. S2† describes the diameter distribution measured for these samples). However, the nanowire density observed on top of the samples appears to increase when the concentration of AuCl₄⁻ is decreased, with values of 2 × 10⁷, 7 × 10⁷ and 10⁸ Si-NWs per cm⁻² for respectively 10, 2 and 1 mM Si-NWs. The variations of these interdependent parameters can be explained by the fact that the larger the initial quantity of gold, the larger the Au–Si droplets will be on the surface of the samples, but this favors also the growth of relatively fewer Si-NWs compared to small Au nanoparticles evenly scattered on the surface of the substrate.

Fig. 2 (a–c) SEM micrographs of bulk Si samples coated with gold using respectively 10 mM, 2 mM and 1 mM AuCl₄⁻ concentrations, (d–f) SEM micrographs of the corresponding 50 μm long Si-NWs after CVD growth, (g) three electrodes cell cyclic voltammetry curves at 1 V s⁻¹ with a 4 V electrochemical window in EMI-TFSI for the corresponding Si-NWs and highly doped flat silicon.

In order to find the most suitable nanostructures for supercapacitors, three electrodes cell experiments were conducted. Fig. 2(g) displays the cyclic voltammetry curves of the different Si-NWs samples and n-doped bulk silicon at a scan rate of 1 V s⁻¹ with a 4 V electrochemical window ([−2.5 V; 1.5 V] vs. Ag⁺/Ag). As reported previously, the silicon electrodes withstand this high voltage window with an almost ideal capacitive behavior.³⁸ The capacitances values derived from CV curves exhibit a rather large enhancement between flat and nanostructured silicon, with values of 5, 180, 280 and 320 μF cm⁻² for bulk silicon, 1, 2 and 10 mM, 50 μm long Si-NWs respectively. The capacitance thus increases with the gold quantity deposited prior to the growth, implying that for 50 μm long Si-NWs, large diameter trunks samples are developing a higher surface area compared to smaller diameter ones.

Trunks and branches optimization

For this systematic study, the previously obtained 50 μm long trunks sample with 3 different morphologies were coated with 1, 2 and 10 mM AuCl₄⁻ gold plating bathes in the same conditions. Several representative gold coated Si-NWs samples are pictured in Fig. 3(a–d). The gold coating process leads to bundling of the nanowires due to capillary forces and liquid bridging between adjacent nanowires during drying, which is a common phenomenon for Si-NWs immersed in aqueous solutions.⁴⁶ The severity of the bundling depends on the sample's nature, especially the diameter of the nanowires, as smaller diameter nanowires are more bendable than large diameter ones (for similar lengths). For instance, with 10 mM trunks, only small bundles of a few nanowires are formed whereas for 1 and 2 mM trunks, the nanowires are crushed in a dense layer of a couple tens of micrometers. Other parameters affect the deposition such as the wettability of the nanowires and the kinetics of electroless reaction which can both affect the quantity of gold depending on the depth of deposition in the nanowires layer. With these phenomena at stake, independently of the gold plating concentration, observations of the 10 mM trunks depicts Si-NWs bundles or standing large diameter (>200 nm) trunks covered with a non-uniform gold layer with large quantities on top of the trunks rapidly decreasing with the distance from the tip of the Si-NWs. Fig. 4(a–d) display a detailed view of a 10 mM Si-NW coated with 10 mM electroless gold, showing that the gold layer shifts from a large dendritic depot on top of the nanowire to small gold particles scattered on the surface 25 μm from the tip to nearly no gold at the bottom of the wire.

Fig. 3 SEM micrographs of various “trunks” samples coated with different quantities of gold, and their corresponding Si-NTrs. (a and b) 10 mM Si-NWs coated with respectively 10 mM and 1 mM AuCl₄⁻, (c) 2 mM Si-NWs coated with 1 mM AuCl₄⁻, (d) 1 mM Si-NWs coated with 2 mM AuCl₄⁻, (e–h) corresponding Si-NTrs after 20 μm long “branches” growth. Same scale bars between Au coated Si-NWs and the Si-NTrs pictures.

Fig. 4 Cross section mosaic SEM micrographs of various Si-NWs and Si-NTrs with different “branches” lengths. (a–c) Magnifications of a gold coated Si-NW (10 mM trunks coated with 10 mM electroless gold) at different distances from the substrate, (d) composite picture of the 50 μm long gold coated 10 mM Si-NW, (e) corresponding Si-NTrs with 5 μm long “branches”, (f) schematic of (e) showing the trunks in dark blue solid line and branches in black dashed line and branches density.

For 1 and 2 mM trunks, the gold deposition consist in a thin layer of crushed gold coated nanowires on top of a subjacent forest with almost no gold deposited in it. The thickness of the subjacent layer can vary depending on the location on the sample between 20 to 40 μm.

For all types of trunks, the quantity of gold deposited on the nanowires decreases with the AuCl₄⁻ concentration, without any fundamental changes in the morphology of the nanostructures or in the distribution of the gold deposit.

Fig. 3(e–h) illustrate the morphologies obtained from the samples displayed in Fig. 3(a–d) after a second CVD step on the gold coated Si-NWs, yielding branches with a maximum length of 20 μm. For large diameter 10 mM trunks, hyperbranched nanostructures were observed regardless of the second gold deposition concentrations, with tree like morphologies and several dozens of branches connected to each trunks and spreading in all directions. The maximum density of secondary growth wires occurs on top of the trunks, with the branches density, diameter and length decreasing with the distance from the tip to the base (Fig. 4(e)). Fig. 4(f) displays a schematic of Fig. 4(e) in order to clarify the complex features of the obtained Si-NTrs. This result is directly related to the gold distribution on the Si-NWs prior to growth with the progressive decrease of the gold quantity from the top to the bottom of the Si-NWs layer. A more detailed study of the branches diameter distribution can be found in the ESI Fig. S4.†

For 1 and 2 mM trunks, the morphologies obtained after the second growth are less prone to natural analogies, with a Si-NWs layer completely covering the subjacent crushed trunks layer. The nanostructures can be divided into a 3 layers stack with, from the substrate to the top: (i) a layer of crushed trunks, (ii) then a dense network of trunks and branches interpenetrated, corresponding to the layer of gold coated trunks previously described, where numerous branches growths were seeded, (iii) and finally on the top, freely grown branches. With this stack structure, top view SEM pictures of the samples only reveal a Si-NWs forest with no distinguishable features of nanotrees (Fig. S5†).

As for the gold deposition step, for each type of trunks, no clear morphological differences can be seen between the nanostructures with 10, 2 and 1 mM branches. The branches may present slightly smaller densities and diameters but the specific surface developed by the different samples cannot be clearly derived solely on the SEM pictures. Especially, the differences in densities and surface coverage of the branches cannot be quantitatively derived. Moreover, the analysis of the 3D interpenetrated Si-NWs network layer obtained with the 1 and 2 mM trunks, and its potentially accessible surface to ions for electrochemical capacitors remains a challenge.

In order to determine which nanostructure is the best for supercapacitor applications, the capacitance values of these nanostructured electrodes were assessed in three electrodes cell, yielding the results exhibited in Table 1. One clear result derived from these measurements is that, regardless of the trunks types, a higher quantity of gold deposited for branches generations yields a larger capacitance value. For 10, 2 and 1 mM trunks, the nanostructures generated with 10 mM branches largely surpasses in capacitance the values obtained with 2 mM which are slightly larger than the ones with 1 mM branches. More surprisingly, at equal branches types, the nanostructures with 10 mM and 2 mM trunks show marginally equal capacitance values, whereas their morphologies greatly differ. These values confirm that the 3D dense interpenetrated Si-NWs network of these samples can provide a significant accessible surface area for supercapacitor devices. However, even-though nanostructures with 1 mM trunks display the same kind of morphologies, capacitances values are significantly lower than for 2 mM trunks, stressing the fact that the balance between trunks' morphologies and branches generation remain complex.

Table 1 Capacitance values in μF cm⁻² of Si-NWs/Si-NTrs samples derived from cyclic voltammetry in three electrodes cell configuration at 1 V s⁻¹ with 4 V electrochemical window (EMI-TFSI, ref. Ag/Ag⁺). “Trunks” and “branches” lengths are respectively 50 μm ± 2 μm and 20 μm ± 1 μm for the longest ones

	Trunks only	10 mM branches	2 mM branches	1 mM branches
10 mM trunks	320	1290	835	780
2 mM trunks	280	1270	805	680
1 mM trunks	180	980	540	505

---

The main outcome of this study is that nanostructures grown using 10 and 2 mM, 50 μm long trunks with 10 mM, 20 μm long branches yielded samples with three electrodes cell capacitance values of about 1.3 mF cm⁻² which is more than 4 times the bare trunks samples capacitance values, and more than 250 times flat silicon capacitance values. Apart from the capacitance values, the electrochemical behaviour of the Si-NTrs is similar to the bare trunks behaviour, showing that the branches addition only enhanced the surface area without significantly changing the electrical characteristics of the electrodes or the properties of the electrode/electrolyte interface.

Branches length optimization

Finally, the length of the branches was studied using one of the optimized nanostructures described in the previous paragraph (10 mM, 50 μm long trunks with 10 mM gold deposition for branches generation). These samples were subjected to the second CVD growth with 5, 12, 21, 49 and 72 μm long ± 1 μm branches growth. Fig. 4(e) portrays the nanostructures obtained after 5 μm long branches growth, and Fig. S3† displays representative samples of the nanostructures obtained for each branches lengths. These SEM characterizations demonstrate the transition between simple Si-NWs in Fig. S3(a)† to Si-NTrs with increasing branches length in Fig. S3(b–d),† to finally ultra-dense 3D interpenetrated Si-NWs networks in Fig. S3(e and f).† This final step can be simply explained by the bridging between nanotrees when the branches length outmatches the distance between adjacent trunks. When this transition occurs, the nanostructures formed are densely interconnected, possibly leading to interesting properties such as mechanical robustness and good electron conductivity within a porous nanostructure.

The three electrodes cell capacitances of nanotrees samples with different branches lengths are shown in Fig. 5(a). Strikingly, the capacitance value of the Si-NTrs with branches only 5 μm long almost doubles compared to the bare trunks samples, exhibiting the large increase of the surface area occurring upon the seeding of branches on the trunks. Moreover, after this large enhancement, the capacitance continuously increases with the length of the branches, with values from 800 μF cm⁻² for 5 μm long branches Si-NTrs to more than 1700 μF cm⁻² for 72 μm long branches Si-NTrs. This extremely high capacitance value remains unmatched to the best of our knowledge for bottom-up silicon based supercapacitive electrodes and represents a large improvement compared to the 900 μF cm⁻² previously obtained for Si-NTrs electrodes.⁴⁰ Fig. 5(b) displays the cyclic voltammetry of these Si-NTrs in regard with the corresponding bare trunks and the bulk silicon, exhibiting the large enhancement of the capacitive behaviour due to the nanostructure optimization.

Fig. 5 (a) Capacitance values for 10 mM/10 mM Si-NTrs in function of branches lengths derived from cyclic voltammetry curves in three electrodes cell at 1 V s⁻¹, EMI-TFSI; (b) cyclic voltammetry curves in the same conditions, of bulk silicon, 10 mM to 50 μm long trunks and 10 mM/10 mM Si-NTRs with 50 μm long trunks and 72 μm long branches.

Full characterization of the optimized Si-NTrs and of the corresponding trunks were conducted in three electrodes cell, as well as in two electrodes “sandwich” type symmetric device. The results of this study are pictured in Fig. 6. The three electrodes cell cyclic voltammetry curves at different scan rates materialize the remarkable capacitive properties of the nanostructured electrodes even at scan rates as high as 10 V s⁻¹, Fig. 6(a). Capacitances values derived from these curves displayed in Fig. 6(b) highlight the retention of capacitance at higher scan rate with 900 μF cm⁻² measured at 10 V s⁻¹ compared to respectively 1.7 and 3.8 mF cm⁻² at 1 and 0.1 V s⁻¹.

Fig. 6 10 mM/10 mM Si-NTrs with 50 μm long trunks and 72 μm long branches electrochemical characterization in EMI-TFSI: (a) cyclic voltammetry curves at different scan rates in three electrodes cell; (b) capacitance values derived from the capacitive current at −0.5 V from (a); (c–f) symmetric 1 cm² sandwich device characterization: (c) galvanostatic charge/discharge at different current densities; (d) capacitance retention during galvanostatic charge/discharge cycling at ±1 mA cm⁻² with a 4 V electrochemical window, (e) Nyquist impedance spectroscopy plot at OCP between 10 mHz and 400 kHz (inset showing the high frequency region), (f) phase angle of the impedance versus frequency.

Symmetric device measurements indicate a nearly ideal capacitive response with triangular shaped galvanostatic charge/discharge cycles at different current densities (Fig. 6(c)), with capacitances as high as 350 μF cm⁻² from CV at 1 V s⁻¹ as well as galvanostatic charge/discharge cycles at 1 mA cm⁻². The capacitance fades from single electrode to a symmetric device of nearly a factor of 5, exceeding the theoretical value of 2. One possible explanation may be that the partial wetting of the electrodes by the ionic liquid contained in the soaked separator resulting in a decreased accessible surface area. Another explanation is that the pressure applied to the nanostructures during cell assembly crushes the nanostructures, although no clear evidence of mechanical modifications can be seen on tested electrodes. The cycling ability of the optimized Si-NTrs devices is displayed Fig. 6(d), with an excellent capacitance retention of 80% after one million galvanostatic cycles of charge/discharge (4 V, 1 mA cm⁻²), following the same cycling behaviour that previously reported Si-NWs supercapacitor devices.^39,40 Electrochemical impedance spectroscopy (Fig. 6(e and f)) denotes an equivalent series resistance of 17 Ω and a relatively short characteristic time⁴⁷ of 32 ms (−45° phase angle frequency of 31 Hz). These measurements lead to values of 235 mW cm⁻² maximum power density, and energy densities ranging from 2.8 mJ cm⁻² to 2.3 mJ cm⁻² at power densities of respectively 2 mW cm⁻² and 30 mW cm⁻², which are extremely interesting values for typical micro-supercapacitor applications.

The same characterizations were conducted on the bare trunks and are displayed in ESI Fig. S6.†

Energy and power densities performances of the optimized trunks and Si-NTrs are plotted in Fig. 7, in addition to our first results in the field of Si-NWs based supercapacitors and other state-of-the-art results for purely double layer micro-supercapacitor. This Ragone plot clearly shows the tremendous improvements due to the nanostructures optimization, with final results for optimized Si-NTrs in the same order of magnitude than state of the art carbon based micro-supercapacitor devices.

Fig. 7 Ragone plot of state of the art silicon based supercapacitor devices (squares) in comparison with previously reported VLS Si-NWs and the present work symmetric supercapacitor devices performances with 10 mM 50 μm long trunks and the corresponding 10 mM/10 mM Si-NTrs with 72 μm long branches (circles). State of the art carbon-based micro-supercapacitors are also pictured for reference (crosses). The number of cycles before a 20% capacitance fade tested for each device is added in brackets.

Conclusions

A systematic study of different key growth parameters for Si-NWs and Si-NTrs was conducted, based on an efficient electroless gold deposition method. 50 μm long Si-NWs displayed an increase of their mean diameters and capacitance values with the quantity of gold deposited prior to CVD growth, with samples reaching up to 60 times the capacitance of flat bulk silicon. Moreover, large diameter trunks were proven more suitable for further branching while the Si-NTrs capacitance expanded with the quantity of gold deposited on the trunks. Finally, raising the branches length increased the capacitance to unprecedented values for bottom-up silicon nanostructures up to 1.7 mF cm⁻² in three electrodes cell (350 times bulk silicon capacitance). These optimized nanostructures were used in symmetric devices that reached excellent properties, with a 350 μF cm⁻² capacitance, a 4 V wide electrochemical window, a high stability over a million of charge/discharge cycles and lastly large values of energy and maximum power density, reaching 2.8 mJ cm⁻² and 235 mW cm⁻² respectively. Such promising results for an all silicon supercapacitor device path the way for tremendous application in the field of integrated micro-power sources, and needs further development for direct integration on chip.

Acknowledgements

The authors would like to thank the French Agence Nationale de la Recherche funding the ISICAP project, the Direction General de l’Armement and the CEA for financial support. The authors would also like to thank Maxime Boniface for HR-STEM imaging of Si-NWs samples.

Notes and references

1. Y. Gogotsi and P. Simon, Nat. Mater., 2008, 845–854.
2. M. Beidaghi and Y. Gogotsi, Energy Environ. Sci., 2014, 7, 867.
3. D. Pech, M. Brunet, H. Durou, P. Huang, V. Mochalin, Y. Gogotsi, P. L. Taberna and P. Simon, Nat. Nanotechnol., 2010, 5, 651–654.
4. F. Beguin, V. Presser, A. Balducci and E. Frackowiak, Adv. Mater., 2014, 26, 2219–2251.
5. P. Huang, D. Pech, R. Lin, J. K. McDonough, M. Brunet, P.-L. Taberna, Y. Gogotsi and P. Simon, Electrochem. Commun., 2013, 36, 53–56.
6. D. Pech, M. Brunet, P.-L. Taberna, P. Simon, N. Fabre, F. Mesnilgrente, V. Conédéra and H. Durou, J. Power Sources, 2010, 195, 1266–1269.
7. H. Durou, D. Pech, D. Colin, P. Simon, P.-L. Taberna and M. Brunet, Microsyst. Technol., 2012, 18, 467–473.
8. H. Xing, X. Wang, C. Shen and S. Li, Micro Nano Lett., 2012, 7, 1166–1169.
9. B. Hsia, J. Marschewski, S. Wang, J. B. In, C. Carraro, D. Poulikakos, C. P. Grigoropoulos and R. Maboudian, Nanotechnology, 2014, 25, 055401.
10. M. Beidaghi and C. Wang, Adv. Funct. Mater., 2012, 22, 4501–4510.
11. D. Aradilla, M. Delaunay, S. Sadki, J.-M. Gérard and G. Bidan, J. Mater. Chem. A, 2015, 3, 19254–19262.
12. Z. S. Wu, K. Parvez, X. Feng and K. Mullen, Nat. Commun., 2013, 4, 2487.
13. S. Li, X. Wang, H. Xing and C. Shen, J. Micromech. Microeng., 2013, 23, 114013.
14. J. Chmiola, C. Largeot, P. L. Taberna, P. Simon and Y. Gogotsi, Science, 2010, 328, 480–483.
15. T. Brousse, D. Bélanger and J. W. Long, J. Electrochem. Soc., 2015, 162, A5185–A5189.
16. X. Wang, Y. Yin, X. Li and Z. You, J. Power Sources, 2014, 252, 64–72.
17. C.-C. Liu, D.-S. Tsai, D. Susanti, W.-C. Yeh, Y.-S. Huang and F.-J. Liu, Electrochim. Acta, 2010, 55, 5768–5774.
18. I. Nam, G. P. Kim, S. Park, J. Park, N. D. Kim and J. Yi, Nanoscale, 2012, 4, 7350–7353.
19. J. Han, Y.-C. Lin, L. Chen, Y.-C. Tsai, Y. Ito, X. Guo, A. Hirata, T. Fujita, M. Esashi, T. Gessner and M. Chen, Adv. Sci., 2015, 2, 1500067.
20. D. P. Dubal, D. Aradilla, G. Bidan, P. Gentile, T. J. S. Schubert, J. Wimberg, S. Sadki and P. Gomez-Romero, Sci. Rep., 2015, 5, 9771.
21. A. Achour, J. B. Ducros, R. L. Porto, M. Boujtita, E. Gautron, L. Le Brizoual, M. A. Djouadi and T. Brousse, Nano Energy, 2014, 7, 104–113.
22. E. Eustache, R. Frappier, R. L. Porto, S. Bouhtiyya, J.-F. Pierson and T. Brousse, Electrochem. Commun., 2013, 28, 104–106.
23. R. Lucio-Porto, S. Bouhtiyya, J. F. Pierson, A. Morel, F. Capon, P. Boulet and T. Brousse, Electrochim. Acta, 2014, 141, 203–211.
24. D. Aradilla, G. Bidan, P. Gentile, P. Weathers, F. Thissandier, V. Ruiz, P. Gomez-Romero, T. J. S. Schubert, H. Sahin and S. Sadki, RSC Adv., 2014, 4, 26462–26467.
25. M. Ertas, R. M. Walczak, R. K. Das, A. G. Rinzler and J. R. Reynolds, Chem. Mater., 2012, 24, 433–443.
26. D. Aradilla, D. Gaboriau, G. Bidan, P. Gentile, M. Boniface, D. Dubal, P. Gomez-Romero, J. Wimberg, T. J. S. Schubert and S. Sadki, J. Mater. Chem. A, 2015, 3, 13978–13985.
27. C. Meng, J. Maeng, S. W. M. John and P. P. Irazoqui, Adv. Energy Mater., 2014, 4, 1301269.
28. H. Han, Z. Huang and W. Lee, Nano Today, 2014, 9, 271–304.
29. S. Desplobain, G. Gautier, J. Semai, L. Ventura and M. Roy, Phys. Status Solidi C, 2007, 4, 2180–2184.
30. A. P. Cohn, W. R. Erwin, K. Share, L. Oakes, A. S. Westover, R. E. Carter, R. Bardhan and C. L. Pint, Nano Lett., 2015, 15, 2727–2731.
31. L. Oakes, A. Westover, J. W. Mares, S. Chatterjee, W. R. Erwin, R. Bardhan, S. M. Weiss and C. L. Pint, Sci. Rep., 2013, 3, 3020.
32. F. Gao, G. Lewes-Malandrakis, M. T. Wolfer, W. Müller-Sebert, P. Gentile, D. Aradilla, T. Schubert and C. E. Nebel, Diamond Relat. Mater., 2015, 51, 1–6.
33. K. Grigoras, J. Keskinen, L. Grönberg, J. Ahopelto and M. Prunnila, J. Phys.: Conf. Ser., 2014, 557, 012058.
34. J. P. Alper, M. Vincent, C. Carraro and R. Maboudian, Appl. Phys. Lett., 2012, 100, 163901.
35. J. P. Alper, S. Wang, F. Rossi, G. Salviati, N. Yiu, C. Carraro and R. Maboudian, Nano Lett., 2014, 14, 1843–1847.
36. F. Thissandier, P. Gentile, N. Pauc, T. Brousse, G. Bidan and S. Sadki, Nano Energy, 2014, 5, 20–27.
37. F. Thissandier, A. Le Comte, O. Crosnier, P. Gentile, G. Bidan, E. Hadji, T. Brousse and S. Sadki, Electrochem. Commun., 2012, 25, 109–111.
38. N. Berton, M. Brachet, F. Thissandier, J. Le Bideau, P. Gentile, G. Bidan, T. Brousse and S. Sadki, Electrochem. Commun., 2014, 41, 31–34.
39. D. Aradilla, P. Gentile, G. Bidan, V. Ruiz, P. Gómez-Romero, T. J. S. Schubert, H. Sahin, E. Frackowiak and S. Sadki, Nano Energy, 2014, 9, 273–281.
40. F. Thissandier, P. Gentile, T. Brousse, G. Bidan and S. Sadki, J. Power Sources, 2014, 269, 740–746.
41. Y. H. Ogata, K. Kobayashi and M. Motoyama, Curr. Opin. Solid State Mater. Sci., 2006, 10, 163–172.
42. S. Y. Sayed, F. Wang, M. Malac, A. Meldrum, R. F. Egerton and J. M. Buriak, ACS Nano, 2009, 3, 2809–2817.
43. R. S. Wagner and W. C. Ellis, Appl. Phys. Lett., 1964, 4, 89.
44. P. Gentile, A. Solanki, N. Pauc, F. Oehler, B. Salem, G. Rosaz, T. Baron, M. Den Hertog and V. Calvo, Nanotechnology, 2012, 23, 215702.
45. G. S. Doerk, N. Ferralis, C. Carraro and R. Maboudian, J. Mater. Chem., 2008, 18, 5376.
46. A. S. Togonal, L. He, P. Roca i Cabarrocas and R. Rusli, Langmuir, 2014, 30, 10290–10298.
47. P. L. Taberna, P. Simon and J. F. Fauvarque, J. Electrochem. Soc., 2003, 150, A292–A300.

---

Footnote

† Electronic supplementary information (ESI) available: Diameter distributions for 10/2/1 mM trunks, SEM cross section of 10 mM/10 mM Si-NTrs with different branches lengths, SEM cross section and corresponding branches diameter distributions, SEM views of 2 mM/10 mM Si-NTrs before and after 2^nd CVD and electrochemical characterization of 10 mM trunks. See DOI: 10.1039/c6ra14806a

---