Low-temperature sol–gel processed AlOx gate dielectric buffer layer for improved performance in pentacene-based OFETs

Femi Igbari, Qi-Xun Shang, Yue-Min Xie, Xiu-Juan Zhang, Zhao-Kui Wang* and Liang-Sheng Liao*
Institute of Functional Nano & Soft Materials (FUNSOM), Collaborative Innovation Center of Suzhou Nano Science and Technology, Soochow University, Suzhou, Jiangsu 215123, China. E-mail: lsliao@suda.edu.cn; zkwang@suda.edu.cn

Received 29th January 2016 , Accepted 11th March 2016

First published on 14th March 2016


An approach to achieve improved performance in pentacene-based organic field effect transistors (OFETs) using high-k AlOx prepared by a low temperature sol–gel technique as a thin buffer layer on a SiO2 gate dielectric was demonstrated. The maximum processing temperature for the AlOx thin layer was 150 °C. The resulting all-inorganic SiO2/AlOx bilayer gate dielectric system exhibited a low leakage current density <1 × 10−8 A cm−2 under an applied electric field strength of 1.8 MV cm−1, a smooth surface with an rms of 0.11 nm and an equivalent dielectric constant (k) of 4.13. The OFET fabricated as a result of this surface modification exhibited a significantly improved field effect mobility of 0.81 cm2 V−1 s−1 when compared with a reference device with a SiO2 single layer gate dielectric, which had a lower mobility of 0.28 cm2 V−1 s−1.


Introduction

The unique role played by OFETs has for many years attracted enormous research interest. This is due to the possibility of achieving a low cost, easily processible, flexible and light-weight device with high performance at low temperatures by a solution method.1–4 In order to have an OFET with improved performance, it is important to prepare a high surface quality and uniform thin film gate dielectric that possesses a high-k value.5,6 This type of gate dielectric affords the fabrication of OFET with high field effect mobility (μ), a threshold voltage (Vth) which is close to zero and subthreshold slope (SS) that is as low as possible.

Traditionally, 200 nm to 300 nm thick commercially available or home made silicon oxide (SiO2) film, thermally grown on a heavily doped n or p type silicon (Si) substrate is used as gate dielectric in OFETs.7–9 The k value for SiO2 is <4.0. This presents SiO2 as a low capacitance gate dielectric material which yields an OFET with low performance. The capacitance density of such a material can be improved by either reducing its thickness or increasing its k value as denoted in eqn (1)

 
image file: c6ra02700h-t1.tif(1)
in which Ci denotes the capacitance per unit area, εo is the permittivity of free space (8.85 × 10−12 F m−1), k is the dielectric constant of the material and d is its thickness. Since there is an inverse proportionality between Ci and d (eqn (1)), an extremely thin layer of the gate dielectric (SiO2) is needed to improve its capacitance due to its low-k value. A great deal of care is therefore needed in the preparation of such a film as defects which can lead to high leakage current could be created. This issue can then be effectively addressed by increasing the k value. The surface modification of SiO2 gate dielectric which involves the introduction of a thin buffer layer of another gate dielectric material with high-k value and good surface properties on the SiO2 has been proven to be effective in this regard.10,11 Although this approach leads to a reduction in the total capacitance of the resulting bilayer gate dielectric system as they are connected in series, an increased equivalent k value and excellent surface properties can lead to enhanced field effect mobility in the active layer of the OFETs fabricated. Similar improvements in device performance as a result of the incorporation of bilayer gate dielectric have also been reported in other OFET systems.12–14 It is evident that the gate dielectric buffer layer may be organic or inorganic.

ZrO2,15,16 HfO2,17,18 Al2O3 (ref. 19) and TiO2 (ref. 20) are examples of inorganic high-k dielectric materials. However, for reasons such as interfacial mismatch and large leakage current exhibited by TiO2 due to its high permittivity value and small band gap14 and the formation of grain boundaries due to the low temperature crystallization of HfO2 and ZrO2,21 Al2O3 stands out as the most suitable inorganic metal oxide. Though Al2O3 has a moderate k value compared to the others, it has advantages such as large band gap and excellent thermal stability.22 Bilayer gate dielectric systems based on Al2O3 and their applications in OFETs have been widely reported over the years.23–25 However, an improvement in the performance of pentacene based OFETs due to the formation of SiO2/Al2O3 bilayer gate dielectric system resulting from the introduction of high-k Al2O3 buffer layer with decent surface properties on SiO2 has not been reported. The materials usually employed for this purpose are self-assemble monolayers (SAMs) and polymers26–28 which are organic and generally possess low k-values.

Preparation methods such as radio frequency (r.f.) magnetron sputtering,29,30 atomic layer deposition (ALD),31–33 chemical vapour deposition (CVD)34,35 and solution processing36–39 have been reported for Al2O3 gate dielectric. However, considering the tasking requirements such as high vacuum, high temperature and high cost needed for the sputtering, ALD and CVD methods, the solution processing route stands out as the most desirable as it does not require these conditions.

Though a few reports have been given on the solution processing of Al2O3 as gate dielectric in OFETs, a relatively high processing temperature especially at the annealing stage has so far been a limiting factor. Han et al.37 reported an annealing temperature of 400 °C as the requirement for the decomposition of the organic components in the Al2O3 precursors. 300 °C was also reported by Avis et al.36 has the required annealing temperature for the preparation of Al2O3. Peng et al.39 studied the application of amorphous alumina as gate dielectric in OFETs by demonstrating a facile low temperature solution method for the preparation of this material. They reported a maximum processing temperature of 180 °C. Polymeric nature of precursor materials could enhance the preparation of highly uniform thin buffer layer of Al2O3 on SiO2 by spin coating, thereby forming a bilayer gate dielectric system. This yields an improved equivalent k value for the resulting bilayer gate dielectric. It is known that improvements in the k value and surface properties of a gate dielectric enhance the mobility of the charge carriers in the active layer of an OFET.19,39–42

Solution–gelation (solgel) chemistry offers a mild route to the preparation of metal oxides.45 In this report, solgel chemistry which is based on low temperature polymerization of molecular precursors such as metal alkoxides M(OR)n43–45 via hydrolysis and condensation steps was adopted for the preparation of AlOx. Hydrolysis and condensation of alkoxides usually lead to the formation of metal oxo-polymers.46,47 The resulting polymeric gel was deposited by spin-coating and annealed at a maximum temperature of 150 °C to obtain an off-stoichiometric alumina (AlOx) thin film. Gradual decomposition of the organic components of the polymeric gel was measured as the annealing temperature increased using Fourier transform-infrared spectroscopy (FT-IR). The effect of surface modification on the performance of a pentacene based OFET was then studied by applying a thin film (20 nm) of the prepared AlOx as a top buffer layer on a 200 nm thick SiO2 which served as the bottom layer.

Results and discussion

Material preparation and characterization

The low temperature sol–gel process used in the preparation of our material followed the hydrolysis and condensation reaction pathway as shown in Scheme 1 below:
image file: c6ra02700h-s1.tif
Scheme 1

In Fig. 1(a), an FT-IR spectra showing the gradual decomposition of the organic components in the AlOx thin film is presented. It can be seen that the as-prepared material exhibits a broad peak around 3450 cm−1, a strong peak around 1467 cm−1 and a weak peak at 696 cm−1 for OH stretch and OH bend vibrations. This indicates the presence of OH group in large proportions majorly as a result of the solvent used. Weak peaks around 2935 cm−1 and a strong peak at 1573 cm−1 indicate the presence of C–H bonds as a result of the organic and metal–organic starting materials. C–O bonds in the precursor gel are also indicated by the peaks seen around 1058 cm−1. The stable peak observed at 578 cm−1 is attributed to the Al–O–Al bonds. A reduction in the peak intensities of the organic components can be observed as the annealing temperature increases while the AlOx peak shows a negligible variation in intensity. At 150 °C, there is a complete disappearance of the peaks attributed to the material's organic components leaving only the peak attributed to Al–O–Al.


image file: c6ra02700h-f1.tif
Fig. 1 (a) FT-IR spectra showing the gradual decomposition of the organic components in the low temperature sol–gel processed AlOx thin film during annealing, (b) wide scan XPS analysis showing the chemical composition of the material annealed at 150 °C, (c) the peak for Al 2p core level observed at 74.6 eV binding energy and (d) the annealing temperature dependent peaks for O 1s core level observed at 531.2 eV and 532.2 eV binding energies.

The chemical composition of the material was further analysed by X-ray photoelectron spectroscopy (XPS). The wide-scan XPS spectrum of the thin film annealed at 150 °C (Fig. 1(b)) reveals that the material consists of only Al and O without other hetero elements. The detailed Al spectrum of the thin film annealed at 150 °C (Fig. 1(c)) reveals a peak at 74.6 eV which is attributed to Al 2p core level. Though a peak for Al 2s core level is also observed at 120.1 eV on the wide scan (Fig. 1(b)), it is a common practice to use the Al 2p peak to analyse samples containing aluminum39,48–50 because plasmon loss peaks from the Al 2p transition usually interfere with the Al 2s peak making the quantification of such peak complicated.51 Fig. 1(d) shows the detailed XPS spectra of O 1s core level for AlOx thin film at ambient and at different annealing temperatures. The peaks were further deconvoluted to show the different environments of the O 1s core level at 531.2 eV (Al–O–Al)52 and about 532.2 eV (Al–OH and Al–OR).52,53 These results show that the formation of Al–O–Al bridge is effectively enhanced as the annealing temperature rises from ambient to 150 °C. This is attributed to the formation of more pure Al–O–Al bridge due to the decomposition of the Al–OH and Al–OR components as the anneal temperature increases. This agrees well with the FT-IR results (Fig. 1(a)) as it indicates that the hydroxy and alkoxy groups become unstable at higher temperature and are decomposed. We determined the stoichiometry of the material annealed at 150 °C by investigating the Al[thin space (1/6-em)]:[thin space (1/6-em)]O ratio. This was done by processing the data with the Casa XPS program (Casa Software Ltd, UK). Peak areas for Al 2p and O 1s core levels were determined by employing a Shirley-type background. The relative sensitivity factors (RSF) provided in the software library were used for quantifying elements.

As shown in Table S1, we obtained an Al[thin space (1/6-em)]:[thin space (1/6-em)]O ratio of 1[thin space (1/6-em)]:[thin space (1/6-em)]1.65 which is similar to values earlier reported by Peng et al.39 Although the expected atomic ratio is 1[thin space (1/6-em)]:[thin space (1/6-em)]1.5 for a pure Al2O3, the excess oxygen may be as a result of the flexibility in the variation of chemical compositions of amorphous materials without a significant change in phase.

No obvious diffraction peak can be observed in the XRD pattern of the film annealed at 150 °C (Fig. S2). This confirms the amorphous nature of the material. The FT-IR, XPS and XRD analyses show that a pure off-stoichiometric amorphous AlOx thin film which is suitable for device applications such as gate dielectric in OFETs can be successfully prepared by our method.

It is important that the surface of the material serving as gate dielectric in OFETs be as smooth as possible as the surface properties determine the morphology and the charge carrier mobility of the active layer and the general performance of the device. We therefore conducted a comparative surface scan on the SiO2 layer and the 20 nm AlOx thin film deposited on SiO2 layer and annealed at 150 °C to form a SiO2/AlOx bilayer system. This was done by using AFM in the tapping mode. Fig. 2 shows the AFM images of the two forms of gate dielectric. As seen in Fig. 2(a) the thermally grown SiO2 layer exhibits a greater roughness (rms 0.23 nm) while in Fig. 2(b) the SiO2/AlOx bilayer system exhibits a much lower roughness (rms 0.11 nm). Hence, due to its polymeric nature, the AlOx gel obtained from the low temperature sol–gel process can easily form a uniform and homogenous thin film on the thermally grown SiO2 layer using the spin coating technique. This therefore makes the material suitable for applications as gate dielectric and dielectric buffer layer in OFETs.


image file: c6ra02700h-f2.tif
Fig. 2 Tapping mode AFM surface scan of (a) the SiO2 single layer with a root-mean-square (rms) roughness of 0.23 nm and (b) the 20 nm AlOx thin film deposited on SiO2 layer and annealed at 150 °C with an rms roughness of 0.11 nm.

Material's dielectric properties

To characterize the changes in dielectric properties such as leakage current density and k value of thermally grown SiO2 gate dielectric as a result of the deposition of a top buffer layer of AlOx, simple capacitors having a SiO2 single layer and a SiO2/AlOx bilayer with MIM device structures Si/SiO2/Au and Si/SiO2/AlOx/Au respectively were fabricated. Their current–voltage characteristics and frequency dependent capacitance (CF) curves where obtained. Fig. 3(a) shows the leakage current density as a result of the applied bias voltage for both the SiO2 single layer and the SiO2/AlOx bilayer gate dielectric materials. It can be seen that the SiO2/AlOx bilayer with a field strength of 1.8 MV cm−1 shows better insulating properties with a low leakage current density (<1 × 10−8 A cm−2) while the SiO2 single layer with a field strength of 2 MV cm−1 shows a relatively higher leakage current density (<1 × 10−6 A cm−2). Both measurements were taken by applying a bias voltage of 40 V over a contact area of 0.09 cm2.
image file: c6ra02700h-f3.tif
Fig. 3 (a) The leakage current density as a result of the applied bias voltage for both the SiO2 single layer and the SiO2/AlOx bilayer gate dielectric materials and (b) the frequency dependent capacitance density measured for the device made with SiO2 single layer and SiO2/AlOx bilayer showing standard deviation based on five rounds of measurements in each case.

To prevent the injection of charge carriers into an oxide gate dielectric the band potential barrier must be greater than 1 eV.22 SiO2 which has a band gap of 9 eV could therefore be said to be a suitable gate dielectric material as it has high barriers for electrons and holes. However its k value is considerably low to effectively perform this function. The reduction in leakage current observed for SiO2/AlOx bilayer is due to the increase in thickness of the double layer system and the increase in the equivalent dielectric constant due to the addition of a high-k top layer (in this case AlOx). The tunnelling current in a gate dielectric material decreases exponentially as the thickness and the k value of the dielectric layer increase. Fig. 3(b) shows the standard deviation curves of frequency dependent capacitance of the device made with SiO2 single layer and SiO2/AlOx bilayer. The measurements were repeated five times in each case by applying a zero bias voltage on the Au top electrode while we ground the Si substrate. The capacitance density for both devices were observed to be stable over a wide range of frequencies. Lower capacitance density values were obtained for the bilayer gate dielectric compared to the single layer dielectric. As depicted in eqn (2), this is as a result of the series connection between the SiO2 and AlOx layers.

 
image file: c6ra02700h-t2.tif(2)

Using eqn (1) and averaged Ci of 17.30 nF cm−2 (SiO2) and 16.62 nF cm−2 (SiO2/AlOx) obtained from Fig. 3(b) over a frequency range of 20 Hz to 106 Hz, the extracted k values for the SiO2 (200 nm) single layer and SiO2/AlOx bilayer (220 nm) dielectric are 3.9 and 4.13 respectively. This increased k value in the bilayer alleviates the problem of tunnelling current.

Device properties

To explore the effect of this surface modification of SiO2 gate dielectric, pentacene based OFET was fabricated using the SiO2/AlOx bilayer as gate dielectric (Fig. S1). OFET having SiO2 single layer gate dielectric was also fabricated as a reference device. Characterization was done by using the standard MOSFET model in the saturation region. The devices have a pentacene active layer channel length (L) of 70 μm and a channel width (W) of 1500 μm. 20 devices were fabricated each for the OFETs with and without AlOx buffer layer. The results obtained were averaged and presented in Table 1. Fig. 4(a) and (c) show the room temperature (300 K) transfer characteristics of devices without and with AlOx buffer layer respectively. The transfer characteristics are logarithmic plots of −IDS vs. VGS and plots of (−IDS)1/2 vs. VGS taken at VDS = −30 V. The devices' transfer characteristics were also taken at other temperatures (280 K, 260 K, 240 K, 220 K and 200 K) as shown in (Fig. S3a and b). The room temperature output characteristics of the devices are also presented in Fig. 4(b) and (d). From the parameters obtained we extracted the field effect mobility in pentacene active layer of the devices using eqn (3).
 
image file: c6ra02700h-t3.tif(3)
Table 1 Device parameters of the pentacene based OFETs with SiO2/AlOx bilayer and SiO2 single layer gate dielectrics
Device μ (cm2 V−1 s−1) Vth (V) SS (V per decade) On/off current Vto (V)
With AlOx buffer layer 0.81 ± 0.02 −0.69 ± 0.03 0.10 ± 0.03 1.00 ± 0.1 (×103) 0.20 ± 0.02
Without AlOx buffer layer 0.28 ± 0.04 −2.10 ± 0.06 0.40 ± 0.08 4.00 ± 0.2 (×102) 1.90 ± 0.05



image file: c6ra02700h-f4.tif
Fig. 4 (a & b) The transfer curve and output characteristics of OFET without AlOx buffer layer. (c & d) The transfer curve and output characteristics of OFET with AlOx buffer layer. The transfer curves are logarithmic plots of −IDS vs. VGS and a plot of (−IDS)1/2 vs. VGS taken at VDS = −30 V and the output characteristics represent the drain–source current (IDS) vs. drain–source voltage (VDS) of the devices for each value of gate–source voltage (VGS) which is increased steadily from 0 V to −30 V at an interval of 6 V.

In eqn (3), μ denotes the field effect mobility, Vth, threshold voltage, Cox, capacitance of oxide gate dielectric per unit area, W and L denote the channel width and channel length respectively. Arrhenius plots of the corresponding mobilities as a function of temperature (T) is given in Fig. 5. Therefore, using eqn (4), parameters such as trap free mobilities (μ0) and their corresponding activation energies Ea can be extracted from the plots.

 
μFET = μ0[thin space (1/6-em)]exp(−Ea/KT) (4)


image file: c6ra02700h-f5.tif
Fig. 5 Arrhenius plots of mobilities as a function of temperature for devices fabricated with and without AlOx buffer layer.

K, in eqn (4) is the Boltzmann constant and T is the temperature. It can be seen from Table 1 that the device with AlOx exhibits an averaged mobility value of 0.81 cm2 V−1 s−1 which is almost four times higher than that of the reference device (0.28 cm2 V−1 s−1). It can also be observed that the other parameters show improvements for the device with AlOx relative to the reference device.

The growth of pentacene is known to be sensitive to the gate dielectric surface.54 Since the oxide gate dielectric is in direct contact with the active layer, the charge carrier induction produced by the gate occurs at the active layer/oxide gate dielectric interface. Unlike the polycrystalline SiO2 which could be associated with defects such as oxide grain boundaries, the AlOx prepared and used in this work does not possess grain boundaries as it is amorphous (Fig. S2). This amorphous material has advantages over the polycrystalline SiO2. Such material might be able to configure its interface bonding to minimize the number of interface defects. It is possible to gradually vary the composition of an amorphous oxide without creating a new phase. Amorphous oxides and their dielectric constants are also isotropic, thus fluctuations in polarization from differently oriented oxide grains which could scatter charge carriers does not occur.

Fig. 6 show the morphologies (XRD patterns and AFM images (insets)) of pentacene layer grown on both SiO2/AlOx bilayer and SiO2 single layer gate dielectrics. The same peak pattern was observed for the pentacene layer with and without AlOx underlayer. However, a closer look at the XRD patterns reveals a slight increase in peak intensities for the pentacene layer grown on the SiO2/AlOx bilayer indicating that the AlOx underlayer is favourable for enhanced crystallization of the pentacene layer. Furthermore, it can be seen in the insets of Fig. 6(a) and (b) that the pentacene film has significantly larger grain size on SiO2/AlOx bilayer surface when compared to the film on the SiO2 single layer surface.


image file: c6ra02700h-f6.tif
Fig. 6 XRD spectra of pentacene films grown on: (a) SiO2/AlOx bilayer and (b) SiO2 single layer gate dielectric surfaces. Insets are the corresponding AFM images.

The origin of this variation in pentacene morphology which is a vital factor for charge carrier transport along the pentacene structure can be traced to the surface energies (γs) of the single layer and bilayer gate dielectrics. To obtain γs for SiO2/AlOx bilayer and SiO2 single layer, the contact angles of two test liquids (water and diiodomethane) on the surfaces of the two dielectrics were measured by using a goniometer (G 10, Krüss) equipped with an image capture software (Drop Shape Analysis 1.0 software). As shown in Fig. S4a and b, water contact angles for SiO2/AlOx bilayer and SiO2 single layer were 42.6° and 64.6° respectively.

Diiodomethane also made contact angles of 24.6° and 34.3° on the bilayer and single layer dielectrics respectively. γs for each dielectric was extracted from the Owen, Wendt, Rabel and Kaelble (OWRK) model which is based on Young's equation (eqn (5)) by fitting the measured values of contact angles.54

 
γs = γsl + γl[thin space (1/6-em)]cos[thin space (1/6-em)]θ (5)
where
 
γsl = γs + γl − 2[(γds)1/2(γdl)1/2 + (γps)1/2(γpl)1/2] (6)

In the above equations, γsl denotes the interfacial energy between the solid phase (dielectric surface) and the liquid phase (test liquid), γl is the surface energy of each test liquid and the superscripts d and p in eqn (6) are their dispersive and polar components respectively. The γs value obtained for our prepared SiO2/AlOx bilayer (41.3 mJ m−2) is lower than γs value (48.0 mJ m−2)54,55 reported for pentacene. As a result, the pentacene molecules showed better attraction to the bilayer dielectric surface than they do to each other.

This induced a wider coverage of the resulting large pentacene crystallites on the bilayer gate dielectric as shown in the inset of Fig. 6(a). Conversely, the obtained surface energy for SiO2 single layer (55.8 mJ m−2) is higher than that of pentacene. Consequently, the pentacene molecules exhibited better attraction for each other than for the SiO2 single layer gate dielectric. The pentacene molecules therefore tend to self-assemble as they are deposited on the SiO2 single layer dielectric. This resulted in the formation of small pentacene crystallites (inset of Fig. 6(b)) with enormous volume of grain boundaries which act as traps for charge carriers and contribute to the lower mobility observed in the OFET fabricated without the AlOx buffer layer.

The surface of the underlying gate dielectric layer also has influences on the structural properties of the pentacene crystallites. An induction of structural inhomogeneities in the pentacene crystal structure could lead to limited charge transport.56 Previous studies have shown that hole transport in pentacene crystallites is based on conducting paths formed by π-orbital overlap.57 Such overlap was found to be negligible along the c-axis of the molecule. It was however found to be very effective along the in-plane, ab direction. In addition, herringbone molecular packing have been found to be responsible for different charge transport efficiencies along the face-to-face and face-to-edge orientations of the π-stacking.58

As shown in Fig. 5, it is seen that the mobilities of pentacene-OFETs fabricated on both SiO2/AlOx bilayer and SiO2 single layer exhibited linear Arrhenius relationship with the inverse of temperature (T). This is in accord with previous reports that charge carrier transport in organic semiconductors increases with T.59 This is because charge transport is generally limited by localized trap states which produce a “multiple trapping and thermal release” mode of transport.56 It involves the instantaneous capture of free carriers arriving at traps with a probability close to unity and a thermally-activated release of such trapped carriers.

Therefore, we investigated the origin of improved mobility in the OFET with AlOx buffer layer. This was done by studying the linear relationship between ln[thin space (1/6-em)]μ and 1/T for the pentacene-OFETs formed on SiO2/AlOx bilayer and SiO2 single layer in Fig. 5. The higher Ea (72 meV) observed for the device without AlOx buffer layer corresponds to a broader and deeper trap distribution with respect to the localized energy levels. It shows that there exist numerous grain boundaries (inset of Fig. 6(b)) which lead to more defects in the pentacene layer of the device without AlOx buffer layer, unlike in the device with AlOx buffer layer which exhibited wider coverage and less grain boundary. As a result, there is a reduction of charge carrier transport in the OFET without AlOx buffer layer. This agrees well with previous reports.54,56

The superior surface properties of the amorphous AlOx buffer layer ensures that negligible trapped charges exist in the active layer/gate dielectric interface. This is confirmed by the near zero turn-on voltage (Vto) obtained for the device with AlOx buffer layer (Fig. 4(c)). The improved equivalent dielectric constant of the SiO2/AlOx bilayer gate dielectric allows higher concentration of charge carriers to accumulate in the pentacene active layer for the same applied voltage when compared with the device with single SiO2 layer exhibiting lower k value. This accumulation of the charge carriers causes the Fermi level of the electrodes to move towards the band edge of the active layer. This causes the injection of high density of carriers which are free to move with high mobility into the active layer. Therefore, the SiO2/AlOx bilayer gate dielectric with decent surface properties and improved k value is capable of improving carrier mobility in the pentacene active layer of OFETs.

Conclusion

In conclusion, we have achieved the preparation of an OFET with improved device parameters by carrying out a surface modification of SiO2 gate dielectric. This was made possible by the introduction a low temperature sol–gel processed thin film of amorphous AlOx prepared in this work. The surface modification produced a SiO2/AlOx bilayer system as the gate dielectric. The bilayer dielectric system exhibits a smooth surface with rms of 0.11 nm, an equivalent k value of 4.13, a capacitance density of 16.62 nF cm−2 and a low leakage current density <1 × 10−8 A cm−2. Using the SiO2/AlOx bilayer system as the gate dielectric, the fabricated pentacene-based OFET exhibited a field effect mobility of 0.81 cm2 V−1 s−1. This device performance is improved compared to that of the SiO2 single layer gate dielectric which gave a mobility of 0.28 cm2 V−1 s−1. The surface modification of SiO2 gate dielectric using a low-temperature sol–gel processed amorphous AlOx provides a feasible approach for improving the properties of the gate dielectric and the overall device performance of OFETs.

Acknowledgements

We acknowledge financial support from the Natural Science Foundation of China (No. 61307036 and 61177016) and from the Natural Science Foundation of Jiangsu Province (No. BK20130288). This project is also funded by the Collaborative Innovation Center of Suzhou Nano Science and Technology, the Priority Academic Program Development of Jiangsu Higher Education Institutions (PAPD) and China Scholarship Council (CSC).

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Footnote

Electronic supplementary information (ESI) available: It includes; experimental section, device structure of the pentacene based OFET with AlOx as gate dielectric buffer layer, Table of peak parameters of Al 2p and O 1s core levels and the quantified Al[thin space (1/6-em)]:[thin space (1/6-em)]O ratio in AlOx thin film annealed at 150 °C, XRD pattern of the AlOx thin film annealed at 150 °C confirming the amorphous nature of the material, temperature dependent transfer curves of OFETs with and without AlOx buffer layer and images of contact angle values of water on SiO2/AlOx bilayer, water on SiO2 single layer, diiodomethane on SiO2/AlOx bilayer and diiodomethane on SiO2 single layer. See DOI: 10.1039/c6ra02700h

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