Guodong Wu*ab and
Hui Xiaob
aSchool of Electronic Science and Engineering, Nanjing University, Nanjing 210093, People's Republic of China. E-mail: wuguodong110110@163.com; Tel: +86-25-8359-6644
bNingbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201, People's Republic of China
First published on 7th December 2015
Chitosan is a most common biopolysaccharide and has been widely used for bio- or medical-materials. In this work, chitosan was prepared in the form of self-supported proton-conducting membranes with a high proton conductivity of 2.3 × 10−3 S cm−1 by protonic acid doping at room temperature. These chitosan-based self-supported membranes were then used as both flexible substrates and gate dielectrics for fabricating paste-type thin-film transistors (TFTs). The feature of these paste-type TFTs is that all the electrodes (gate/source/drain electrodes) and channels are located on the same one side of chitosan dielectric membranes, which is very convenient for TFTs to be transferred and stuck on various places in a wide variety of applications. Due to the huge lateral electric-double-layer (EDL) capacitive coupling induced by spatial movement of protons in chitosan-based proton-conducting membranes, these TFTs showed a low-voltage operation of only 1.5 V with a large field-effect mobility of 20.2 cm2 V−1 s−1. Furthermore, AND logic operation was also demonstrated on these TFTs. Our results indicate these chitosan-based paste-type TFTs have great potential for broadening their applications on wearable electronic products and biocompatible electronics.
Chitosan is a biodegradable, biocompatible, nontoxic, and low-cost polymer. They have been widely used for bio- or medical-materials, such as a tissue engineering material, surgical tape, and artificial skin.15–17 Besides, due to its high proton conductivity by acid doping, chitosan has also attracted great attention as solid electrolyte membrane in fuel cells and synaptic transistors.18–20 In this work, in order to reduce the dependence on substrates, chitosan-based biopolysaccharide membranes in self-supported form with high proton conductivity were used as both flexible substrates and gate dielectrics for fabricating paste-type TFTs. These paste-type TFTs feature that all the electrodes (gate/source/drain electrodes) and channels are located on the same one side, which is also treated as special free-standing TFTs. Due to the huge lateral EDL capacitive coupling induced by spatial movement of protons in chitosan-based proton-conducting membranes, these TFTs showed only 1.5 V operating voltage and high-performance electric characteristics. Furthermore, AND logic operation was also demonstrated with double-planar-gate structure on these TFTs.
In general, the ionic conductivity of chitosan in natural state is as low as 10−9 S cm−1 though abundant amino and hydroxyl functional groups exist in chitosan. These groups graft on the polysaccharide framework with strong chemical bonds and they can not work as the mobile ions. However, when the chitosan is doped by acetic acid, the protonation process occurs in chitosan molecules.22 The proton (H+) is dissociated from acetic acid and results free amino group in the chitosan backbone in protonation (–NH2 + HAc ↔ –NH3+ + Ac−). At the same time, the water molecules absorbed in the chitosan chains can form hydrogen-bond sites for the proton transferring from amino groups to water molecules (–NH3+ + H2O ↔ –NH2 + H3O+).23 The specific mechanism of protonation process for chitosan in the acetic acid solution can been seen in our previous report.20 In order to evaluate the proton conductivity of as-prepared self-supported chitosan-based membrane, the Cole–Cole plot was characterized in Fig. 2. Impedance spectroscopy data are collected as real (Re Z′) and imaginary (Im Z′′) components of the complex impedance. The impedance real value (R) of 740 Ω is obtained with the impedance imaginary value equal to zero. The conductivity (σ) could be obtained from the relation below:24
Fig. 3(a) shows the cross-sectional SEM image of the self-supported chitosan-based proton-conducting membrane. Loose microstructure with nanopores is observed, which is favor for proton migration. Inset image in Fig. 3(a) is the higher magnification SEM image. It clearly shows the diameter of the nanopores is ∼300 nm. It is known that the capacitance of dielectrics is a crucial factor for high performance of TFTs.26 In previous studies, vertical sandwich capacitive structure was adopted because bottom-gate or top-gate configuration was always employed in conventional TFTs. Here, in our case, the planar capacitive structure is performed for exploring planar TFTs. As shown in Fig. 3(b), using an planar structure of IZO/chitosan-based proton-conducting membrane/IZO (the distance between coplanar IZO electrodes is 300 μm), the lateral specific capacitance as a function of frequency in the range between 0.1 Hz and 1.0 MHz was measured. It can be seen that the specific capacitance increases with frequency decreasing. The specific gate capacitance is ∼7.6 μF cm−2 at 1.0 Hz. For conventional dielectrics, the lateral capacitive coupling is extremely weak in this 300 μm long distance. Therefore, such huge lateral capacitance is mainly attributed to the lateral movement of protons in chitosan-based proton-conducting membrane and the formation of EDL at the chitosan/IZO electrode interface, as shown in Fig. 3(c).27 The large lateral specific capacitance in self-supported chitosan-based proton-conducting membrane can provide a strong capacitive coupling effect even the long planar distance existed, which is meaningful for fabricating low-voltage and high-performance free-standing planar TFTs. Fig. 3(d) shows that the self-supported chitosan-based membrane has a leakage current below 50 pA with the bias voltage between −1.6 V and 1.6 V, indicating the as-prepared chitosan-based membrane is an electronically insulating but proton-conducting membrane. At the same time, it ensures the leakage current is too small to influence the operation of the as-fabricated TFTs.
Previously, there were a few reports on free-standing TFTs. However, these free-standing TFTs still employed conventional bottom- or top-gate configuration which the gate electrodes and channel layers are separated on the two sides of gate dielectrics.28 Here, making use of the large lateral EDL capacitance in self-supported chitosan-based proton-conducting membrane, free-standing planar TFTs based on the lateral capacitive coupling were fabricated, as shown in Fig. 1(b). Fig. 4(a) shows the output characteristics (Ids − Vds) of these TFTs. The Vgs was varied from −0.4 to 0.6 V in 0.2 V steps. A small hysteresis at high gate voltage is observed due to the mobile protons in self-supported chitosan-based proton-conducting membrane. The Ids − Vds curves of such device have well-defined linear regimes at low Vds biases and saturation regimes at high Vds biases, which is in good agreement with the standard theory of field-effect transistors. It also indicates a good ohmic contact between W probe and IZO source/drain electrodes. Fig. 4(b) shows the corresponding transfer (Ids − Vgs) curves of the device measured on a flat surface and on a convex surface with a bending radius of 20 mm. In the flat state, the curves shows a low off current of ∼0.025 nA with a on/off ratio of 6 × 106. The subthreshold swing was found to be 98 mV per decade. The threshold voltage (Vth) is calculated to be −0.16 V from the x-axis intercept of (Ids)1/2 − Vgs curve (Vds = 1.5 V). The field-effect mobility (μ) can be extracted from the equation in saturation region (Vds > Vgs − Vth): Ids = WCiμ(Vgs − Vth)2/2L,29 where L = 100 μm is the channel length (the distance of two tungsten probes that as the source/drain electrodes), W = 150 μm is the channel width, and Ci = 7.6 μF cm−2 is the specific gate capacitance. Therefore, saturation field-effect mobility (μ) is estimated to be 20.2 cm2 V−1 s−1. The influence of the bending to the electrical properties of the flexible junctionless TFTs is also investigated. The current on/off ratio, subthreshold swing, and field-effect mobility are estimated to be 7 × 106, 100 mV per decade, and 18.1 cm2 V−1 s−1, respectively. Saturation mobility shows a small reduction of 10.3%, and other electrical parameters were almost unchanged. Our results indicate the device exhibits a good electrical stability under applied tensile strains with a convex radius of 20 mm. For conventional TFTs, the channel current is general controlled by vertical capacitive coupling. In our case, the gate voltage directly coupled to the semiconductor channel laterally by only one lateral EDL capacitor. The reason was attribute to the proton lateral hopping between hydroxyl groups and water molecules under applied electric field on planar gate. The static stability measurements on these free-standing planar TFTs were also investigated. Fig. 4(c) the transient response of these TFTs to a square-shaped Vgs with a pulsed amplitude of V+ = 1.5 V and V− = −1.5 V, under a constant bias of Vds = 1.5 V. The device exhibits a good reproducibility because the off current was almost unchanged and the current on/off ratio nearly kept to be a constant (>105). This indicates that protons in the chitosan-based electrolyte have not penetrated into the IZO channel and no obvious electrochemical doping occurs at the IZO channel and chitosan-based electrolyte interface when the gate potential is biased. Notably, in polyelectrolyte-gated field-effect transistors previous reported, the humidity in the atmosphere has an impact on the proton conductivity of chitosan and the response speed of TFT devices.30 Here, in our device, we will further systematically study the polarization mechanism of chitosan-based electrolyte films under different humidity and their influence on the performance of TFT devices in the next step.
Further, with introducing another planar gate, AND logic operation was realized on the free-standing double-planar-gate TFTs. The double-planar-gate configuration was showed in Fig. 1(b), where the two planar gates (G1 and G2) are equivalent and symmetrical. Fig. 5(a) shows the equivalent logic principle of the double-planar-gate TFTs. Different fixed biases applied on two planar gates are characterized as Input 1 and Input 2, while the drain currents are regarded as Output. Fig. 5(b) illustrates the logic performance. HIGH input voltage bias (1.5 V) and LOW input voltage bias (−1.5 V) are denoted as state “1” and state “0”, respectively. The detected HIGH current (>100 μA) and LOW current (<1 nA) are denoted as state “1” and state (“0”), respectively. When both Input 1 and Input 2 are “0”, the Output shows “0”. When both Input 1 and Input 2 are “1”, the Output shows “1”. However, when Input 1 is “1” and Input 2 is “0”, or Input 1 is “0” and Input 2 is “1”, the Output shows “0”. The results strongly indicate that such free-standing double-planar-gate TFTs realize AND logic operation with high on/off ratio of >105 at the range of only 1.5 V.
![]() | ||
Fig. 5 (a) Logic circuit diagram of the free-standing planar TFT with double-planar-gate configuration. (b) Input–output characteristics of the AND logic. |
This journal is © The Royal Society of Chemistry 2015 |