Leakage current characteristics in MOCVD grown InAs quantum dot embedded GaAs metal-oxide-semiconductor capacitor

Abstract

The leakage current characteristics in metal-oxide-semiconductor (MOS) based capacitors, which have direct bearing on the charge retention property in a MOS based memory cell, is analyzed on the basis of the available conduction mechanisms. The current–voltage characteristics have been studied in GaAs MOS capacitors with three different structures such as Al/ZrO₂/GaAs, Al/ZrO₂/(GaP)GaAs, and Al/ZrO₂/InAs QDs/ZrO₂/(GaP)GaAs; the latter two being passivated by an ultrathin GaP interface passivation layer on GaAs. The current density in passivated devices is found to be at least one order of magnitude lower than that in unpassivated devices due to a passivation layer which reduces the surface states. In the case of passivated devices Fowler–Nordheim tunneling is found to be the dominant conduction mechanism, whereas the unpassivated devices follow Poole–Frenkel emission. However the quantum confinement and Coulomb blockade effect in QDs embedded devices play a major role towards decreasing the leakage current density further. The value of the leakage current in the QDs embedded device is found to be the lowest (∼10⁻⁶ A cm⁻²) and the current is primarily controlled by the Fowler–Nordheim tunneling.

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1 Introduction

Semiconductor quantum dots (QDs) have become more and more fascinating nanoscopic structures due to their increasing demand in information storage in non-volatile memory (NVM) applications.^1–3 NVM devices are used as a main component in all types of portable electronic gadgets such as solid state disks, smart phones, tablet PCs, etc. Most of the commercially available memory devices consist of a metal-oxide-semiconductor (MOS) structure. In such MOS devices due to the gradual leakage of charges through tunneling, the retention behavior of the memory cell degrades. Moreover the presence of fixed oxide charges, trap charges between the oxide–semiconductor interface, oxide trap charges, and mobile ionic charges will lead to a significant increase in the leakage current density in these devices.^4–8 However by means of proper surface passivation the density of interface trap charges can be reduced, which contributes positively towards decreasing the leakage current.^9–12 In case of MOS based memory devices with embedded low dimensional structures as charge storing elements, the lateral charge spreading, Coulomb repulsion, and carrier tunneling through the oxide potential barrier are responsible for the gradual leakage.^13–16 However due to continuous downscaling of microelectronics devices, the demand for high-k materials are gradually increasing to replace conventional Si oxide based gate dielectrics. It may be mentioned here that unlike SiO₂ based MOS device, the high-k materials with less thickness leads to significant reduction in leakage current density while maintaining the same capacitance value. Several reports are available in the literature on various high-k gate dielectrics such as HfO₂,¹⁷ Al₂O₃,¹⁸ TiO₂,¹⁹ CeO₂,²⁰ Y₂O₃,²¹ Ta₂O₅,²² and rear earth based binary and ternary oxides²³ to ensure good quality and defect free interface with GaAs. Among them ZrO₂ is one of the most promising candidate, which possesses certain advantages such as high dielectric constant (∼25), a high break down field (7–15 MV cm⁻¹), large bandgap (5.8 eV), and thermodynamically stable.²⁴ On the other hand compound III–V semiconductors such as GaAs with high-k dielectrics have the potential to replace Si as a channel material in metal-oxide-semiconductor-field-effect-transistors (MOSFET) due to their high intrinsic electron mobility and lower effective mass.^25–29 However, the fabrication of GaAs MOS based devices remains a challenge due to poor GaAs/oxide interface. Direct deposition of high-k dielectric layer on GaAs does not facilitate stable and defect free interface due to the presence of surface states as a result of Ga–O or As–O bonds which will lead to large surface recombination velocity and Fermi level pinning. So proper surface passivation is essential for the fabrication of high performance and stable GaAs based MOS devices. Hence to eliminate the native oxide formation and to unpin the Fermi level, in this work, an ultra-thin GaP layer was grown on GaAs.

In the literature various studies are available on the MOS based memory devices where metallic nanoparticles,^30,31 semiconducting nanocrystals (NCs),^32,33 and quantum dots³⁴ were used as storing elements. In these reports the authors systematically studied the memory characteristics of the devices. However, the authors did not report on the nature of the leakage current through the devices and how it affects the device performance in terms of retention characteristics. In addition, it is important to note that leakage of charges through tunneling barrier affects the retention characteristics of a memory device to a great extent. Direct tunneling enhances the leakage, i.e. charge loss in a memory device, whereas in case of Fowler–Nordheim (F–N) tunneling the carriers cannot tunnel directly; rather they tunnel through a triangular potential barrier.^35,36

Keeping in view of the above perspectives, in this work, we have, thus, investigated the carrier transport, vis-a-vis leakage current characteristics in GaAs MOS capacitors with three different distinct structures, viz. Al/ZrO₂/GaAs, Al/ZrO₂/(GaP)GaAs, and Al/ZrO₂/InAs QDs/ZrO₂/(GaP)GaAs taking into consideration the available theoretical approaches of conduction mechanisms.

2 Experimental

p-Type (100) GaAs substrates, having carrier concentration of 1 × 10¹⁶ cm⁻³, were chemically surface treated by boiling sequentially with acetone and methanol followed by rinsing repeatedly in deionized water (18.2 MΩ). Then the substrates were dipped into the etchant solution of H₂O₂–NH₄OH–H₂O (1 : 1 : 2 by volume) to remove native oxides and elemental As. After that those were rinsed for 3 min in deionized water and dried by N₂ gun. An ultrathin interface passivation layer (IPL) of GaP of thickness 1.5 ± 0.3 nm was grown on p-GaAs at 540 °C by metal organic chemical vapor deposition (MOCVD) technique. Tri-methyl gallium (TMGa) and phosphine (PH₃), with a flow rate of 6.8 sccm and 70 sccm, respectively, were used as the precursors for Ga and P, respectively, whereas high purity H₂ was used as carrier gas. At the same time the control samples without any passivation layer were also kept for further processing. Then ZrO₂ (8 nm thick) was grown on both the passivated and control samples using reactive rf-sputtering technique at a substrate temperature of 22 °C for 5 min. The flow rate of argon and oxygen were taken as 10 and 40 sccm, respectively, in the reactive plasma at a pressure of 5.0 torr. Subsequently another set of devices were fabricated where InAs QDs were grown on tunnel ZrO₂ (of thickness 4.8 nm) deposited onto GaP passivated GaAs substrate at 500 °C for 3 min by MOCVD technique. Tri-methyl indium (TMI) and arsine (AsH₃) were utilized as the precursor source for In and As, respectively, whereas high purity H₂ was taken as carrier gas. The flow rate of TMI and AsH₃ were taken as 45 and 75 sccm, respectively. At the end of the growth of InAs QDs, the samples were kept inside the reactor for post deposition annealing (PDA) at 500 °C for 3 min under the over pressure of arsine (AsH₃). Likewise, ZrO₂ control layer having thickness of 25 nm was grown onto it. The grown ZrO₂ film was annealed at 500 °C for 5 min in N₂ ambient. Top gate electrode of Al covering an area 1.96 × 10⁻³ cm² was formed in all the samples by thermal evaporation. Similarly a low resistance ohmic contact was made with Pd–Ag onto the back surface of GaAs for the samples. Finally the samples were subjected to post metallization annealing (PMA) at 300 °C for 3 min in argon ambience. The thickness of the deposited layers was determined by an ellipsometer (Accurion Nanofilm EP3 Model). The schematic of the fabricated GaAs MOS based devices is shown in Fig. 1(a)–(c). The QDs grown on tunneling layer were characterized by atomic force microscopy (AFM) (model 5100, Agilent Technologies) in order to determine their size and density. The devices and InAs QDs were characterized by cross-sectional transmission electron microscope (TEM, FEI-Tecnai G220S-Twin) and high resolution TEM (HRTEM, Jeol Jem-2100), respectively. The chemical analysis of ZrO₂ layer and QDs was performed by X-ray photoelectron spectroscopy (XPS) using PHI 5000 VersaProbeII (ULVAC-PHI, INC, Japan) system connected with a microfocused (100 μm, 25 W, 15 kV) monochromatic Al Kα source (hν = 1486.6 eV), a hemispherical analyzer, and a multichannel detector. During the analysis, the vacuum was maintained at ∼10⁻¹¹ torr inside the chamber. To neutralize the charge, a combination of low energy Ar⁺ ions and electrons were used throughout the analysis. Charge calibration of the binding energy scale was done by C 1s peak at 284.6 eV. The electrical measurements of the memory devices were carried out using Keithley (4200-SCS) semiconductor parameter analyzer.

Fig. 1 A schematic of GaAs MOS devices (a) without GaP passivation layer, (b) with passivation layer, and (c) with InAs QDs.

3 Results and discussion

Cross-sectional transmission electron microscopy images of the structures (a) ZrO₂/GaAs, (b) ZrO₂/(GaP)GaAs, and (c) ZrO₂/InAs QDs/ZrO₂/(GaP)GaAs are shown in Fig. 2(a)–(c) respectively. From the images all the individual layers are clearly visible in a stacked structure. Each layer is marked and denoted separately in order to visualize the successive layer by layer deposition. As shown in Fig. 2(c), InAs QDs grown on tunnel ZrO₂ layers are non-uniformly diffused into the control ZrO₂ layers. It is due to the annealing of capping ZrO₂ layer at a temperature of 500 °C for 5 min. However after the end of the growth of InAs QDs, the samples were kept inside the reactor for PDA at 500 °C for 3 min under the over pressure of AsH₃, which promotes the random distribution of the QDs. The annealing temperature as well as the annealing duration in both the cases is high enough for the non-uniform distribution of the QDs in the ZrO₂ layer. It may be mentioned here that the InAs QDs embedded structures were also subjected to PMA at 300 °C for 3 min, which further play a significant role for the migration of the QDs.

Fig. 2 Cross-sectional TEM images of the structures (a) ZrO₂/GaAs, (b) ZrO₂/(GaP)GaAs, and (c) ZrO₂/InAs QDs/ZrO₂/(GaP)GaAs.

The HRTEM and AFM images of the InAs QDs are shown in Fig. 3(a) and (b), respectively. From Fig. 3(a), approximately round-shaped and spot like quantum dots are distinctly visible with diameter about 5 nm. As shown in Fig. 3(b), homogeneous distribution of dots over the surface of high-k is clearly visible. The dot height and density were determined to be 3–10 nm and 1.8 × 10¹¹ cm⁻², respectively.

Fig. 3 (a) HRTEM and (b) AFM images of InAs QDs grown by MOCVD technique at 500 °C for 3 min.

The chemical nature of InAs QDs and ZrO₂ was analyzed by high resolution XPS measurements. As depicted in Fig. 4(a), two distinct peaks of In 3d spectrum of the InAs QDs are observed. The one located at 443.80 eV belongs to In 3d_5/2, while the other at 451.40 eV corresponds to In 3d_3/2. Thus the value of spin orbital splitting (SOS) was found to be 7.60 eV.

Fig. 4 X-ray photoelectron spectra of (a) In 3d and (b) the As 3d region of InAs QDs.

Fig. 4(b) shows the signature of two peaks of As. The peak at 41.40 eV is related to As whereas that at 44.40 eV denotes the oxidized As. The As peak was found to be more stronger than that obtained from the oxidized species. The spectrum of Zr 3d signal of ZrO₂ films is shown in Fig. 5(a). Two peaks of Zr 3d signal corresponding to Zr 3d_5/2 and Zr 3d_3/2 are located at 182.80 eV and 185.10 eV. The SOS value was found to be 2.3 eV which assured the fully oxidation state of Zr (Zr⁴⁺).³⁷ The presence of O 1s core level spectrum at 532.15 eV as shown in Fig. 5(b) again confirms the formation of ZrO₂ film.

Fig. 5 X-ray photoelectron spectra of (a) Zr 3d and (b) O 1s of ZrO₂ thin films.

The leakage current of the devices were measured with respect to the positive voltage applied to the gate electrode. The current density in Al/ZrO₂/(GaP)GaAs devices was found to be lower (∼10⁻⁵ A cm⁻² at 1 V) than that in Al/ZrO₂/GaAs (∼10⁻⁴ A cm⁻² at 1 V) as shown in Fig. 6. The ultrathin interface passivation layer of GaP reduces the formation of surface states such as Ga (Ga–O) and As oxides (As–O). So the generation of Ga and As antisite defect states between ZrO₂ and GaAs is minimized. As a result the leakage current density in GaP passivated (Al/ZrO₂/(GaP)GaAs) devices was found to be at least one order of magnitude lower than that in unpassivated (Al/ZrO₂/GaAs) devices.

Fig. 6 J–V characteristics corresponding to the leakage current of Al/ZrO₂/GaAs and Al/ZrO₂/(GaP)GaAs.

In order to understand the electric field dependence of the carrier transport, the J–V characteristics as shown in Fig. 6, were analyzed on the basis of the available conduction mechanisms. The carrier injection processes can be represented by the Poole–Frenkel (P–F) emission and Fowler–Nordheim (F–N) tunneling, which can be mathematically expressed as follows³⁸

where I denotes the current through the device, C and C₁ are constants, V is the bias, q is the electronic charge, K is the Boltzmann constant, T is the absolute temperature, ∅ is the potential barrier height, ε is the dynamic permittivity, d is the tunneling distance, and m* is the effective mass of charge carriers. As shown in Fig. 7(a), there exists a linear relationship between ln(J/V) and V^1/2 following (1) in the bias range 0.2 to 5 V and thus in this voltage range the conduction is dominated by the Poole–Frenkel (P–F) emission in unpassivated devices with structures Al/ZrO₂/GaAs. However P–F emission is a bulk-limited transport mechanism dominated by the field enhanced thermal emission of trapped charges.³⁹ Charges are trapped into the insulator by the impurity levels and transported to the insulator conduction band by the internal emission process. Application of field facilitates the distortion in potential well associated with the traps and increases the possibility of trapped charges to escape. Therefore P–F emission is referred to as field assisted thermal detrapping of the carriers from the bulk oxide. We have further investigated the transport mechanism in passivated devices, viz. Al/ZrO₂/(GaP)GaAs. In this case ln(J/V²)–(1/V) plot, as shown in Fig. 7(b), follows a linear relationship in the voltage range of 2–0.2 V which indicates that the conduction mechanism is primarily due to the F–N tunneling. During F–N tunneling the electrons are able to tunnel through a triangular potential barrier into the conduction band of oxide following quantum mechanical phenomena.³⁸ Thus it is observed that the current conduction follows Poole–Frenkel emission in the unpassivated devices, whereas it is due to Fowler–Nordheim tunneling in case of passivated devices. Now to estimate the leakage current in InAs QDs embedded devices with structure Al/ZrO₂/InAs QDs/ZrO₂/(GaP)GaAs, the current density–voltage (J–V) characteristics was studied and shown in Fig. 8(a). The value of the leakage current was measured to be 3.11 × 10⁻⁶ A cm⁻² at −1 V, which is found to be the lowest among the values found in other devices. This low value of leakage current is attributed to Coulomb blockade effect which in turn is promoted by the size quantization of the dots. It may be mentioned here that this effect becomes significant when the total capacitance of the QDs is sufficiently small. The Coulomb blockade effect prevents electrons to enter further into the InAs QDs, since in that case the addition of single electron requires sufficiently high charging energy. This facilitates low leakage current density in the QDs embedded devices.⁴⁰

Fig. 7 (a) Variation of ln(J/V) with V^1/2 for the Al/ZrO₂/GaAs capacitor, and (b) variation of ln(J/V²) with (1/V) for the Al/ZrO₂/(GaP)GaAs. Symbols are the experimental data fitted with solid straight lines using available conduction mechanisms.

Fig. 8 (a) J–V characteristics corresponding to leakage current, and (b) variation of ln(J/V²) with (1/V) of InAs QDs based MOS devices. Symbols are the experimental data fitted with solid straight lines using available conduction mechanisms.

In addition, GaAs surface passivation by ultrathin GaP layer reduces the interface states, which decreases the leakage current further. Again the current density–voltage characteristics exhibit a linear relation between ln(J/V²) and (1/V) following (2) in the bias range 4–0.8 V as shown in Fig. 8(b). This gives a clear notion that the current conduction in the QDs embedded devices is caused by the F–N tunneling of charge carriers. Here the stored charges into the potential well of the InAs QDs region will tunnel either to the gate or to the GaAs channel by surmounting a triangular potential barrier following F–N tunneling. With increase in the effective oxide thickness at 5 nm or above (4.8 nm tunnel oxide thickness plus 1.5 nm GaP interface passivation layer), the Fowler–Nordheim tunneling (triangular potential barrier) is dominant with the degradation of trap assisted tunneling at a fixed oxide field. However at higher voltage and above a particular thickness of the tunnel oxide layer the oxide band bending takes place due to the generation of field gradient. So the electrons cannot tunnel directly to the other side of the barrier; rather they tunnel through a triangular potential barrier from GaAs inversion layer to the conduction band of the ZrO₂ layer and then transported to the QDs. Thus ln(J/V²) vs. 1/V curve shows linearity in the high voltage region (deviates linearity in the low voltage region) and the Fowler–Nordheim tunneling dominates in the bias range 4.0–0.8 V as shown in Fig. 8(b). The ultrathin interface passivation layer of GaP suppresses the generation of As oxides and Ga high valance oxides with significant reduction in interface states and defects between ZrO₂ and GaAs, resulting in decrease in leakage current. Moreover P–F emission is a bulk-limited transport mechanism dominated by the field enhanced thermal detrapping of the carriers from the bulk oxide as shown in Fig. 9(a). The carrier transport phenomenon through a triangular potential barrier during F–N tunneling is illustrated in Fig. 9(b). The conduction mechanisms, viz. P–F emission in the unpassivated devices and F–N tunneling in the QDs embedded devices are found to be consistent with the reports available in the literature for the structures Pt/ZrO₂/n-GaAs and Al/HfO₂/p-Si, respectively.^41,42

Fig. 9 Schematic of the conduction mechanism during (a) P–F emission and (b) F–N tunneling.

4 Conclusion

In conclusion, the current–voltage characteristics of MOS capacitors with structures ZrO₂/p-GaAs, ZrO₂/GaP/p-GaAs, and ZrO₂/InAs QDs/ZrO₂/GaP/p-GaAs were systematically analyzed to understand and control the leakage current behavior in these devices. The current density in the devices passivated with ultrathin GaP is found to be one order of magnitude lower than that in the unpassivated devices. This is due to passivation of p-GaAs surface with ultrathin GaP layer which effectively suppressed the formation of interface states and thus facilitated significant improvement in electrical characteristics in terms of reduced leakage current density. Detail analysis on the leakage current characteristics in GaAs MOS capacitors shows that the carrier transport in unpassivated devices follows Poole–Frenkel emission, whereas Fowler–Nordheim tunneling is the dominant conduction mechanism for passivated devices. However in case of quantum dots embedded devices the value of the current density was measured to be ∼10⁻⁶ A cm⁻², which is observed to be the lowest leakage current in comparison to all the devices in the present study. The low value of leakage current is attributed to Coulomb blockade effect which is further promoted by the size quantization. Fowler–Nordheim tunneling is the dominant current conduction mechanism in the devices containing QDs due to formation of triangular potential barrier at the conduction band of oxide.

Acknowledgements

One of the authors (S. M. Islam) acknowledges University Grants Commission, New Delhi for awarding Maulana Azad National Fellowship for Minority Students.

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