Pranab Kumar Sarkara,
Snigdha Bhattacharjeea,
Manoj Prajapatb and
Asim Roy*a
aDepartment of Physics, National Institute of Technology Silchar, Silchar-788010, Assam, India. E-mail: 28.asim@gmail.com
bDepartment of Physics, Indian Institute of Science Education and Research (IISER) Bhopal, Bhopal – 462066, Madhya Pradesh, India
First published on 3rd December 2015
We report the electrical bistable characteristics of a hybrid polymer/inorganic nanocomposite device consisting of SnO2 nanoparticles (NPs) embedded in an insulating polymethylmethacrylate (PMMA) layer sandwiched between conductive indium tin oxide (ITO) and aluminium (Al) electrodes. X-ray diffraction measurements were performed for assessment of the crystallographic nature of SnO2 nanoparticles while the microstructural nature of SnO2 nanoparticles embedded in the PMMA matrix was confirmed using transmission electron microscopy. Detailed electrical characterizations suggested an influence of the NP concentration on the switching characteristics of the Al/SnO2-PMMA/ITO memory devices. The highest resistance ratio > 103 (Roff/Ron) was observed in a device with 2 weight% SnO2 NPs. The retention tests on the fabricated device demonstrated the consistency in current of the ON/OFF state even after 104 s. The conduction mechanisms of the fabricated nanocomposite based memory cell were discussed on the basis of experimental data using a charge trapping–detrapping mechanism in the NPs. Our findings offer a feasible and low cost chemical approach to fabricate a transparent and high density RS memory device.
In this paper, we report on the fabrication of OBDs with Al/SnO2-PMMA/ITO structure at different concentrations of SnO2 NPs by using a simple spin-coating method. The 2 wt% SnO2 NPs embedded OBD exhibits good optical-transparency of ≈80% in the visible region with a high on/off ratio of 103, high cell-to-cell uniformity and long term stability. Based on the experimental observations, the electrical properties of the as-fabricated devices are systematically investigated and a model for the switching phenomena is demonstrated. The present SnO2 NPs embedded devices are of great potential for future transparent electronic applications.
D = kλ/βcosθ | (1) |
Fig. 3(a) shows the TEM image of several SnO2 NPs and inset figure represents the histogram of the NP diameter distribution. The size of the SnO2 NPs is approximately 14 nm. Fig. 3(b) shows the cross sectional TEM image of 2 wt% SnO2 NPs – PMMA layer. A high-resolution TEM (HRTEM) image (inset of Fig. 3(b)) establishes arbitrary distribution of the SnO2 NPs in the PMMA layer which may affect the electrical performance of the memory device. Energy dispersive spectroscopy (EDS) analyses reveal that the constituent elements of the NPs are Sn and O2, as shown in Fig. 3(c). Fig. 3(d) illustrates the selected area electron diffraction (SAED) pattern of aggregated NPs, whose diffraction rings from outside to inside can be indexed as (211), (200), (101) and (110) planes of rutile phase SnO2, respectively.
To analyze the switching performance, the dc I–V characteristics of SnO2 NPs embedded devices have been studied. Fig. 4(a) distinctively displays bipolar resistive switching (BRS) characteristics in Al/SnO2-PMMA/ITO memory cells with concentrations of SnO2 NPs 0.5, 1, 2 and 3 wt%. The arrows in Fig. 4 indicate the voltage sweep direction. For the Al/SnO2 (2 wt%)-PMMA/ITO device, starting with the high resistance state (HRS) the current increased slowly with the applied negative voltage (sweep 1) and switched to the low resistance state (LRS) at −3.9 V. The LRS can be retained after removing the voltage supply (sweep 2) and switching back (erasing process) to HRS under a positive bias (3.4 V) on TE (sweep 3). Since PMMA acts as an insulating material,22 the I–V characteristics of Al/SnO2-PMMA/ITO device would be dominated by the number density of SnO2 NPs. Indeed, ON/OFF state currents depend on the wt% of SnO2 NPs, as shown in Fig. 4(b). The current in LRS tends to increase with increasing concentration of SnO2 NPs. On the contrary, it has been observed that maximum resistance (Roff/Ron) ratio is obtained for the device with 2 wt% than that for 3 wt% because of large aggregations of SnO2 NPs inside the insulating layer makes a robust conductive channel between the electrodes under the applied electric field.22,26,40
In order to know more about the charge transport mechanism for the OBDs with concentration of 2 wt% SnO2 NPs, the (I–V) curve was re-plotted in the log scale [Fig. 5(a and b)]. When a small negative bias voltage was applied to the pristine Al/SnO2-PMMA/ITO device in its initial HRS, ohmic conduction was observed, as shown in Fig. 5(a).2,10,13,14,29,31 Moreover, (I–V) curve at very low applied bias (0 to −0.45 V) in the HRS could be fitted by using TE process, as shown in inset of Fig. 5(a). This suggests that the charge transport at very low voltage is also governed by the thermal emission of charge carriers over the energy barrier between Al and PMMA when the barrier is not too high for thermal injection.17 With the increase of electric field from −1.3 V to −2.9 V, the number of injected electrons becomes comparable with the thermally generated free electrons.29 Therefore, the electronic transport was predominated by injected electrons which are partly trapped at the interface Al/PMMA.18,41,42 As a result the carrier conduction strays significantly from ohmic conduction, giving rise to space-charge-limited-current (SCLC) conduction behaviour with slope ∼2, (Fig. 5a).10,12,13,18,31 The results indicate that the captured carriers in SnO2 NPs embedded PMMA matrix can act as space charges. The electron mobility value of SnO2 NPs blended PMMA thin film is found to be 1.3 × 10−12 m2 V−1 s−1 by using the following eqn (2)
(2) |
With further increase of applied bias up to −3.9 V, steep current flows through the device with large linear slope value of 4 [Fig. 5(a)].10,14,19,31 Interestingly, the SnO2 NPs are playing the role as the traps sites which are able to hold the charges very firmly, as proven from long retention test (Fig. 7(b)).12,41 Once all the traps of SnO2 are completely filled up, the OBD switch to the LRS. As a result, the LRS conduction regains the ohmic [Fig. 5(a)] nature with slope ∼1.5,10,12,14,15,18,31 Fig. 5(b) shows the similar kind of behaviour in positive bias region that was observed in case of negative bias condition in the RS devices. Fig. 5(c) shows the capacitance–voltage (C–V) at high frequency (500 kHz) for the SnO2 NPs embedded OBD. The calculated value of dielectric constant of SnO2 NPs embedded PMMA thin film is found to be ∼6. The large hysteresis in C–V curve indicates that trapping regulates the memory effect of SnO2 NPs embedded PMMA device.43 The charge trapping density for SnO2 NPs blended PMMA device is estimated to be 2.1 × 1012 cm−2 by using the following equation43
(3) |
To investigate the memory performance of Al/2 wt% SnO2-PMMA/ITO structure, we performed a series of characterizations such as statistical distributions of LRS/HRS and SET/RESET voltage, endurance and retention test. Fig. 6(a) shows the distributions of VSET/VRESET for the Al/SnO2-PMMA/ITO OBDs during the device-to-device (D/D) operation. For D/D the mean values (μ) and standard deviations (σ) of VSET and VRESET are −3.6 V, 3.5 V and 0.37, 0.34, respectively. Small values of σ indicate less spreading in distribution of SET/RESET voltage which indicates the uniform distribution of SnO2 NPs throughout the PMMA matrix. Fig. 6(b) also indicates uniform cumulative distribution of RLRS/RHRS of the hybrid SnO2-PMMA switching devices during the cycle-to-cycle (C/C) and (D/D) operation. The mean values (μ) of RLRS and RHRS are 96 and 69.4 kΩ and 170 and 193 MΩ for (C/C) and (D/D) operation, respectively. Due to high resistance ratio (HRS/LRS > 103), the device has potential for use in RS memory application with enhanced data storage capacity. The endurance and retention properties of both 1 and 2 wt% SnO2-NPs embedded memory cells are illustrated in Fig. 7. Fig. 7(a) represents the repetitive sweeps; this consists of write, erase, and read cycles for the selected cell of 1 and 2 wt% SnO2 NPs blended memory device. During the endurance test, OBDs maintained their HRS/LRS ratios of over ∼103 without showing any substantial electrical degradation. Fig. 7(b) shows a good retention property with a rewriting capability over a 104 s test period of 1 and 2 wt% SnO2 NPs embedded OBDs.
In order to study the observed memory characteristics, we considered the work function of Al and ITO electrodes44 and energy gap between the highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) of PMMA44 and the electronic structure of conduction and valence band of SnO2,45 as shown in Fig. 8(a). The energy barrier between the electrodes and the conduction band of SnO2 is smaller than that of the electrodes and the valence band of SnO2.18,46 Thus, for both forward and reverse applied bias, electron injection is more favorable over holes injection from the electrode. However, since the barrier between ITO and SnO2 NPs (0.5 eV) is greater than that between Al and SnO2 NPs (0.1 eV), electron injection efficiency from ITO electrode is relatively lower than that from Al electrode to SnO2. As a result difference in trapping and detrapping processes are observed under the forward and reverse voltage sweep.11,43 The current conduction process in the Al/SnO2-PMMA/ITO device is mainly governed via charge trapping mechanism by the SnO2 NPs associated with the filamentary conduction mechanism due to local degradation of PMMA layer.18,22,41,44,46 On the basis of the aforesaid discussion, the write/erase operational mechanism of the switching memory device is elucidated in Fig. 8(b)–(d). When low electric field is applied to the Al electrode the OFF state current increases with decreasing trap depth. This is because of the low electron occupation probability in the trap with a shallow depth. Therefore, free electron density increases and the HRS current in low voltage (∼−1 V) can be attributed to the ohmic process. At higher voltage region (−1 V < V < −3 V) the electrons existing at the conduction band of SnO2 are transported along the direction of the applied electric field by the trapped charge limited current (TCLC) conduction process.41,44 The electric field among adjacent SnO2 NPs increases with the increase of applied voltages.46 Hence, the SnO2 NPs act as electron trapping sites due to the lower energy levels of SnO2 between the PMMA layers and the space charge formation by electron trapping dominates the conduction process.22,46 However, the SnO2 NPs in the HRS are partly occupied as some of the trapped electrons are emitted from the SnO2 NPs to the ITO electrode, as shown in Fig. 8(b).18,41 When the applied voltage is very high (≥−3.9 V) the free electron density is very large due to high injection current. Consequently, the electron occupation probability becomes larger as the Fermi level moves to the LUMO level of PMMA.47 As a result band bending of PMMA at PMMA/Al interface is much more than that of PMMA/ITO interface. Even though the trap depths are different, all traps under high voltages are completely occupied by electrons, resulting in an increase in film conductivity.12,18,41,46 Therefore, SnO2 embedded PMMA based memory device with different trap depths exhibit the same ON-state current characteristics under high voltages (−3.9 to −5 V). As a result device switches from the OFF state to the ON state. This bistable transition is known as writing process for the memory devices, as shown in Fig. 8(c). The LRS current is attributed to the ohmic process by trap filled states and filamentary channels by localized degradation of polymer layer.12,18,46 After the applied voltage is withdrawn, the device can remain in the LRS which is indicative of nonvolatile nature of the Al/SnO2-PMMA/ITO device. Subsequently, when a positive voltage is applied to the Al electrode, OBD retains in LRS until the reset voltage of 3.4 V is reached. Nevertheless, at a higher voltage (>3.4 V) the electron captured in the SnO2 NPs are detrapped under reverse electric field, as shown in Fig. 8(d), and is known as erasing process. Eventually, this causes a significant decrease in the current and the OFF state re-appears in Al/SnO2-PMMA/ITO memory device.18
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