High-k double gate junctionless tunnel FET with a tunable bandgap

Abstract

In the present work, the performance of a heterostructure double gate junctionless tunnel FET (HJL-DGTFET) having a tunable source bandgap has been analyzed using a 2D simulation technique. The tunable source HJL-DGTFET shows a high ON-current (≈ 6.5 × 10⁻⁵ A μm⁻¹) and a very low OFF-current (≈ 4.8 × 10⁻¹⁷ A μm⁻¹). The device shows a point subthreshold slope ≈ 36.2 to 26.8 mV per decade and the average subthreshold slope ≈ 86.1 to 84.2 mV per decade for 0.0–40.0% Ge-mole fractions at room temperature with an I_ON/I_OFF ratio of 10¹². The excellent switching characteristics and steeper subthreshold slope at room temperature indicate that this is a promising candidate for the replacement of bulk MOSFETs. In this article, the optimization of device parameters such as the oxide thickness (t_ox), gate dielectric material and spacer has also been discussed in detail.

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1 Introduction

In recent years, green transistors have attracted a lot of attention as a replacement for aggressively scaled conventional bulk MOSFETs for low power applications. The rapid down-scaling of conventional bulk MOSFETs below 45 nm introduced undesirable effects such as gate leakage current, short channel effects (SCEs) and hot carrier effects (HCEs), which led to extreme degradation in the device performance.¹ One of the fundamental limits of conventional MOSFETs is a subthreshold slope (SS) at room temperature with a minimum value of 60 mV per decade which can be obtained from:^1,2where Ψ_s is the surface potential, V_g is the gate voltage, C_ox is the oxide capacitance, C_d is the depletion capacitance and K_BT/q is the thermal voltage (26 mV per dec at 300 K).

In the down-scaling approach, conventional Si MOSFETs are approaching the end of the technology roadmap. To overcome this limitation, various alternative devices are being proposed such as multigate MOSFETs (FinFET and gate all around FETs) and ultra-thin body (UTB) devices. These proposed devices could be less attractive in the ultra scaled regime to fulfill the need of low power applications such as computer and mobile technology.^3–6 For low power applications, the subthreshold slope (see eqn (1)) plays a very significant role.¹ The electrical characteristics of TFETs are less influenced by short channel effects (SCEs)^7–11 and also break the physical limitations of bulk MOSFET, due to SS < 60 mV per dec at room temperature. The lower subthreshold slope value for TFETs allows power supply (V_DD) scaling. The scaling of supply voltage improves the leakage power reduction (P = I_OFF × V_DD) for TFET devices in comparison to bulk MOSFETs.²

The heterostructure double gate junctionless tunnel FET (HJL-DGTFET) is an improved version of the conventional TFET. The HJL-DGTFET does not have a P–N junction at the source/channel and channel/drain interfaces, and as a result has a lower value of leakage current than conventional TFETs.^12–15 The silicon based TFETs have a large bandgap and as a result have low band-to-band (B2B) tunneling and a lower drive current (I_ON). To improve the drive current of TEFTs, silicon germanium (Si_1−xGe_x) alloys and III–V semiconductor-based low bandgap TFETs have been demonstrated.^16,17

In this paper, a HJL-DGTFET with an improved device performance is suggested for low power applications. In this device, the impact of the germanium mole fraction, oxide thickness, gate spacer and gate oxide material on the device performance has been studied and discussed in detail.

2 Adoption of tunable band behavior in JL-TFET

The TFET devices, comparatively, have a small leakage current and a low subthreshold slope against the bulk MOSFETs, but suffer from a low on-current (I_ON). To improve the I_ON of TFETs, various approaches such as a heterostructure source/channel, a low bandgap semiconductor, high-k gate materials and the inclusion of strain effect have been adopted. The bandgap of HJL-DGTFET at the source/channel interface is transformed into a tunable form by using band engineering via the epitaxially grown (Si_1−xGe_x) layer on silicon. The epitaxially grown (Si_1−xGe_x) layer on silicon creates a lattice mismatch between Si/(Si_1−xGe_x); as a result, strain originates at the interface. The lattice constant of (Si_1−xGe_x) with a particular mole fraction of germanium could be calculated by Vegard’s rule¹⁸ as follows:

a_SiGe = a_Si + x(a_Ge − a_Si), (2)

where a_Si is the lattice constant for silicon, a_Ge is the lattice constant for germanium, x is the mole fraction of Ge in (Si_1−xGe_x) and a_SiGe is the lattice constant for (Si_1−xGe_x). The induced strain at the Si/(Si_1−xGe_x) interface due to lattice mismatch reduces the effective bandgap between the conduction band of the channel and the valence band of the source in the tunneling region. The effective Ge-mole fraction dependent bandgap of the tunneling region in HJL-DGTFET is calculated from:^19–23

E^SiGe_g = 1.084 + 0.42x, (3)

where E^SiGe_g is the bandgap for the (Si_1−xGe_x).

3 Band-to-band-tunneling current modeling approach

The schematic of the HJL-DGTFET device used in the study is shown in Fig. 1. In the HJL-DGTFET, current conduction strongly depends on the tunneling width (λ) and is controlled by the gate voltage. The band diagrams of the device for the off-state and the on-state are shown in Fig. 2(a) and (b) respectively. The tunneling of charge carriers in the device strongly depends on the bandgap (E_g) (see Fig. 2). The epitaxially grown (Si_1−xGe_x) alloy on silicon causes a compressive strain on both Si and (Si_1−xGe_x). The induced strain in the alloy modifies the band-structure as well as the bandgap of Si_1−xGe_x which can be calculated by eqn (3) with the Ge-mole fraction. In the tunneling region of HJL-DGTFET, at the heterostructure source/channel interface, Si_1−xGe_x has a smaller bandgap than silicon; as a result, the tunneling probability will be increased. The tunneling probability for the HJL-DGTFET can be predicted in a simplified manner by the Wetzel–Kramers–Brillouin (WKB) approximation as follows:where T(E) is the tunneling probability, E_g is the bandgap, q is the universal charge constant, m* is the effective mass and t_ox, t_Si, ε_ox and ε_Si are the gate oxide thickness, the semiconductor thickness and the dielectric constants of the oxide and semiconductor materials, respectively. The tunneling window (Δϕ) in the tunneling probability is written as follows:²⁴

Δϕ = E^ch_V − E^S_C. (5)

Fig. 1 Schematic view of the heterostructure double gate junctionless Tunnel FET (HJL-DGTFET).

Fig. 2 (a) Energy band-diagram at V_GS = 0.0 V and (b) energy band-diagram at V_GS > 0.0 V for HJL-DGTFET.

Fig. 2(a) and (b) show the turn-off and turn-on characteristics for the studied HJL-DGTFET respectively. These figures indicate that the turn-on and turn-off characteristics of HJL-DGTFET are governed by the applied gate voltage. The carrier transport in TFET is mainly due to band-to-band tunneling between the source and the channel region. As shown in Fig. 2, only the electrons which have a higher energy than the source/channel interface barrier width can enter into the channel region from the source and get collected at the drain node.

4 Results and discussion

The device used in the study has a gate length of 20 nm and a channel thickness of 5 nm, with uniform doping of 1.0 × 10¹⁸ cm⁻³ in the entire device (see Fig. 1). The HJL-DGTFET device has two types of gate: a control gate and an auxiliary gate, and the corresponding values of the work function used in the study for them are 4.2 eV and 5.2 eV. The device physics of HJL-DGTFET are different from the conventional bulk MOSFET. The current conduction in the HJL-DGTFET device is entirely dependent on the tunneling width, and the tunneling width dependence on the device parameters such as t_ox, ε_ox, bandgap (E_g) and effective mass (m*) is comprehensively presented in this section.

As the Ge-mole fraction in the Si_1−xGe_x semiconductor increases, the effective tunneling width in the tunneling region at the Si/Si_1−xGe_x interface reduces due to the compressive biaxial strain between Si_1−xGe_x and Si. Due to this, the tunneling probability increases; as a result, the tunneling current also increases. The tunneling width (λ) variation against the Ge-mole fraction is shown in Fig. 4. The impact of the germanium mole fraction on the current is shown in Fig. 3.

Fig. 3 Turn-on characteristics of JL-TFET for various Ge-mole fractions in the (Si_1−xGe_x) source. The device is biased by the control gate, auxiliary gate and drain-source voltage at V_GS = 0.0 V to 1.0 V, V_G−aux = 0.0 V and V_DS = 1.0 V.

Fig. 4 Impact of the Ge-mole fraction on the effective tunneling width of applied voltages: V_GS = 1.0 V, V_DS = 1.0 V and V_gate−aux = 0.0 V.

The impact of the Ge-mole fraction on the internal electric field along the channel is shown in Fig. 5. The effective electric field across the tunneling junction is shown in Fig. 5, and the results improved the B2B tunneling current as shown in Fig. 3. The electric field inside the tunneling junction was also accompanied with a rise in the tunneling current in the OFF-state. The OFF-state (I_OFF) and ON-state (I_ON) current variation versus the Ge-mole fraction for HJL-DGTFET is shown in Fig. 6. The (I_ON) and (I_OFF)-current variation versus the Ge-mole fraction illustrates that during device fabrication, the Ge-mole fraction in the source plays a significant role for an optimized device response. Around 30% Ge-mole fraction for the adopted device shows optimized device performance, but a higher germanium mole fraction (>30%) reduces the band to band tunneling. A Ge-mole content with around 25–35% compressive strain gives the lowest (I_OFF).¹¹ Due to the ultra thin double gate TFET structure, electrons are quantized and quantum confinement results in an effective bandgap increase.

Fig. 5 Electric field distribution with various Ge-mole fractions for the same V_GS = 1.0 V, V_DS = 1.0 V, with a high-k HfO₂ gate dielectric material with work functions ϕ_Gate = 4.2 eV and ϕ_auxiliary = 5.2 eV.

Fig. 6 Impact of the Ge-mole fraction (x) on the turn-on and off-characteristics on JL-TFET on source: (Si_1−xGe_x).

Other device characteristics associated with the adopted HJL-DGTFET are the point subthreshold slope and the average subthreshold slope. The value of the point subthreshold is calculated by:

where S_point is the point subthreshold slope, I_DS is the drain current and V_GS is the applied gate voltage, and the average subthreshold slope is calculated as follows:where V_T is the threshold voltage, V_Goff is the gate voltage at which the drain current starts to rise, I_OFF is the drain current at V_GS = V_OFF and I_T stands for the tunneling current.

The impact of the Ge-mole fraction on the point subthreshold slope is shown in Fig. 7. The reduced point subthreshold with a higher content of germanium shows that the tunneling current increases with an increase in the Ge-mole fraction. The reduction in the average subthreshold slope with an increase in the Ge-mole fraction shows the scalable property of the power supply voltage (V_DD), which in turn reduces the leakage power. The internal potential variation along the channel is shown in Fig. 8 and the potential variation for the tunneling region is shown in Fig. 9. The plot in Fig. 9 is for the on-state condition for a Ge-mole fraction of 0.0–40% in the source for V_GS = 1.0 V, V_G−aux = 0.0 V and V_DS = 1.0 V. The internal potential variation is showing a similar trend to that of the energy bandgap with the Ge-mole fraction. The shift in internal potential with the Ge-mole fraction along the channel (see Fig. 8 and 9) also shifts the electron and hole concentrations in the device as shown in Fig. 10.

Fig. 7 Impact of the Ge-mole fraction on the point-subthreshold slope (left) and the average-subthreshold slope (right).

Fig. 8 Internal potential variation inside the device and the effect of the Ge-mole fraction for the applied biasing voltages: V_GS = 1.0 V, V_DS = 1.0 V and V_{G−auxiliary} = 0.0 V for HfO₂ as the gate dielectric material with a 2 nm physical thickness.

Fig. 9 Internal potential variation inside the tunneling region for V_DS = 1.0 V, V_GS = 1.0 V, V_G−aux = 0.0 V with Ge-mole fraction variation.

Fig. 10 Electron-hole concentration profile along the channel versus Ge-mole fraction for V_DS = 1.0 V.

The impact of the spacer length, oxide thickness and gate dielectric constant on the device performance is shown in Fig. 11–18. Fig. 11 shows the effect of the spacer length variation on the turn-on characteristics of HJL-DGTFET. The contribution of the field line passing through the spacer region to the total field lines in the tunneling region varies with the spacer length, which in turn affects the tunneling probability. As a result, the on-state current (see Fig. 11), as well as the subthreshold slope (see Fig. 12), varies with the variation in spacer length.

Fig. 11 Turn-on characteristics for various gate spacers in the control and the auxiliary gate.

Fig. 12 Variation of the point subthreshold slope (S_point) and the average subthreshold slope (S_average) with a gate spacer.

The impact of oxide thickness (t_ox) is shown in Fig. 13–15. Similar to the conventional MOSFETs, the gate oxide thickness plays a very crucial role in the tunneling phenomenon through capacitive coupling. The variation in tunneling current with oxide thickness is shown in Fig. 13 for a Ge-mole fraction of 30%, V_DS = 1.0 V, V_G−aux = 0.0 V at T = 300 K. It shows that a thicker gate oxide has a lesser impact on the tunneling current than a thinner gate oxide due to the lower capacitive coupling. The variation of t_ox also influences the tunneling probability according to the WKB approximation (see eqn (4)), due to modulation in the tunneling width. A thicker gate oxide (t_ox) increases the tunneling width (λ) and the vice versa happens for a thinner gate oxide as follows:

Fig. 13 Tunnel current response, I_DS with respect to the applied control gate voltage at V_{G−auxiliary} = 0.0 V and V_DS = 1.0 V for different oxide thicknesses.

The reduction in oxide thickness increases the on-state current as well as the off-state current, as shown in Fig. 14. The off-state current in the thinner gate oxide increases due to an increase in the gate leakage current. The decrease in the gate oxide thickness also improves the point subthreshold slope, as well as the average subthreshold slope, due to the improvement in the on-state current (see eqn (6) and (7)) as shown in Fig. 15.

Fig. 14 The I_ON and I_OFF current variation at V_DS = 1.0 V for different high-k gate oxide thickness.

Fig. 15 The point and average subthreshold slope variation with high-k gate oxide thickness at applied V_DS = 1.0 V for 30% Ge-mole fraction.

The influence of the gate dielectric constant (ε_ox) is shown in Fig. 16. From eqn (8), it is clear that a higher value of ε_ox (i.e. high-k materials) reduces the tunneling width, which in turn improves the non-local tunneling rate (see Fig. 16) according to the WKB approximation. The improvement in the on-state characteristics with high-k gate oxide materials is shown in Fig. 17. The high-k gate dielectric materials also increase the leakage current due to strong coupling between the gate and the tunneling region.¹⁶ The adopted HJL-DGTFET shows a very weak dependence of leakage current (I_OFF ≈ 10⁻¹⁶ A μm⁻¹ to 10⁻¹⁷ A μm⁻¹) with an increase in the gate dielectric materials (k = 3.9 to 25). The dependency of the gate dielectric material on I_OFF and the point subthreshold slope (S_point) is shown in Fig. 18. It shows that the use of a low-k gate dielectric material leads to a poor point subthreshold slope in comparison to the high-k.

Fig. 16 The impact of various high-k gate dielectric materials such as: SiO₂ (ε_r = 3.9), Si₃N₄ (ε_r = 7.0), Al₂O₃ (ε_r = 9) and HfO₂ (ε_r = 25) on the band-to-band tunneling rate.

Fig. 17 Impact of gate dielectric materials on the tunneling current, I_DS for applied terminal voltages: V_DS = 1.0 V, V_auxi = 0.0 V with t_ox = 2 nm.

Fig. 18 Point-subthreshold (S_point) and the I_OFF current variation versus high-k gate dielectric materials at room temperature for V_DS = 1.0 V, V_GS = 1.0, and V_G−aux = 0.0 V.

5 Conclusions

In this paper, a comprehensive analysis of a 20 nm double gate HJL-DGTFET is presented. In the analysis, the impact of material parameters such as the germanium mole fraction, the gate oxide thickness, the dielectric constant and the spacing between the auxiliary and control gate on the device performance is presented in detail. It is observed that the Ge-mole fraction plays a significant role in the improvement of the HJL-DGTFET performance with a high-k gate dielectric material. In the study we have found that the device with a 30% Ge-mole fraction for a 2 nm oxide thickness shows very good I_OFF ≈ 4.8 × 10⁻¹⁷ A μm⁻¹, I_ON ≈ 6.5 × 10⁻⁵ A μm⁻¹, and subthreshold slope characteristics (S_point ≈ 36.4 mV per dec and S_average ≈ 82.4 mV per dec with V_DS = 1.0 V).

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