Size effect of InAs quantum dots grown by metal organic chemical vapor deposition technique in storing electrical charges for memory applications

Abstract

Catalyst-free growth of InAs quantum dots (QDs) with different sizes and densities was undertaken by metal organic chemical vapor deposition technique to investigate their capability and the effect of size on charge storage. The QDs were grown on a high-k dielectric, ZrO₂, layer, which was deposited onto the GaAs substrate passivated with an ultra-thin GaP layer. The size and density of the QDs were controlled by varying the growth temperature. To demonstrate the effect of QD dot size on charge storage behavior, they were used as charge storing nodes in a GaAs metal-oxide–semiconductor based memory device. From capacitance–voltage measurements, it was observed that the hysteresis width of the device and the density of stored charge increase with a decrease in size of the QDs. This is due to size quantization, for which the surface potential as well as the generation of strongly localized trap levels become significant. On the other hand, the charge retention is found to increase on increasing the dot size due to enhanced conduction band offset between the QDs and the substrate, in which tunneling back the stored carriers is minimized.

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1 Introduction

The quantum size effect (QSE) is one of the most pronounced effects in quantum confined semiconductor nanostructures when the size of the nanocrystals (NCs) is smaller than the electron de Broglie wavelength. QSE facilitates the formation of electric dipoles, redistribution or localization of the energy levels, and leads to a discrete density of states along the confinement direction.

However, the quantum size effect causes widening of the bandgap as well as a change in the density of states of the semiconductor NCs. Moreover, due to the size effect, the variation of surface potential promoted by electrostatic coulomb charging is observed along with carrier tunneling. Size quantization favors the charging of discrete energy levels of the NCs and when the total capacitance of the NCs is sufficiently small, the coulomb blockade effect becomes significant. The coulomb blockade effect prevents further electron to tunnel into the NCs because in that case addition of single electron requires sufficient charging energy. Coulomb blockade effect, thus, minimize the leakage current by reducing the carrier tunneling. Therefore, the QSE plays a crucial role on the capacitance of a semiconductor NCs and thus the charge storage properties of the NCs are affected to a great extent.

Recently, effect of particle size on the resonant tunneling phenomena in CdS nanoparticles (NPs) based electrical bistability devices was reported by Nenna et al.¹ The current conduction and negative differential resistance behavior produced by resonant tunneling effect was significantly enhanced due to the formation of quantized energy levels by decreasing the size of the CdS NPs. Yun et al.² reported the size dependent single electron tunneling phenomena in Pt NPs embedded metal-oxide–semiconductor (MOS) structure at room temperature. On reducing the (Pt) particle size, the single electron addition energy (coulomb charging energy) has been found to increase leading to larger tunneling current. The QSE on the surface potential of nanocrystalline Si based thin film transistor was reported by Mao.³ Here the change in surface potential of the Si–NCs was investigated due to the change in bandgap as well dielectric constant with the grain size. The dependency of gate leakage current on the grain size of Si–NCs was also studied by Mao.⁴ Here the author demonstrated that the tunneling current of Si thin film transistor strongly depends on the size of Si–NCs due to the change in surface potential.

Though some reports are available in the literature about the size effect of nanostructures on charge storage, most of these devices are based on the Si metal-oxide–semiconductor (MOS) structure using Si⁵ and Ge NCs.^6,7 It is found from these reports that the stored charge density and the carrier dynamics in terms of charge retention time were uniquely controlled with the size of NCs in the memory devices. However due to superior electron transport properties, viz. high electron mobility and high break down field of GaAs compared to Si; GaAs MOS based structures are considered to be a better choice for new generation low-power and high-speed memory applications.^8–10 In order to reduce the operating voltage various high-k dielectric materials, viz. HfO₂, ZrO₂, Al₂O₃, Y₂O₃, TiO₂, and LaAlO₃ are used in the MOS structures.^11–17

In the literature various studies are available where semiconductor nanostructures such as Si,¹⁸ Ge,^19,20 SiGe QDs,²¹ Si nano-needles,²² and carbon nanotubes²³ were used as charge storing nodes. Metallic nanoparticles of Ni,²⁴ Pt,²⁵ cobalt silicide (CoSi₂),²⁶ vanadium silicide (V₃Si),²⁷ and AuPd,²⁸ and dielectric NCs (such as Al₂O₃ nanodots),²⁹ were also used as charge storing elements. In these reports, though the authors studied the charge storing capability of NCs, QDs, and metallic NPs, the effect of size quantization is not investigated. Moreover use of metallic nanoparticles leads to reaction between the metal and oxide. In some cases, metal might diffused into the oxide matrix and due to high temperature processing, it gets ionized leading to doping the gate, source or drain region.³⁰ Moreover obtaining stable metal NPs with repeatability is not an easy task. Furthermore any application with metal NPs does not fit in the existing process lines of IC technology. Thus semiconducting QDs are good substitutes for metal NPs as charge storage elements since the former has certain advantages of high exciton binding energy, minibands, and large discrete density of states which makes it suitable for multibit storage. Reports are available where single layer InAs QDs was used as charge storage nodes in GaAs/AlGaAs heterostructure.³¹ However type-I nature of InAs/GaAs heterostructure promotes rapid unwanted radiative recombination of carriers. As a result charge storage relaxation takes place, which deteriorates the charge retention characteristics of the memory devices.

In order to achieve good retention property, it is important to have high conduction band offset between QDs and the high-k dielectric materials in MOS based memory devices along with good interface quality with the tunnel layer. It is well known that like SiO₂/Si, the direct deposition of high-k dielectric layer on GaAs does not facilitate stable and defect free interface due to the presence of surface states as a result of Ga–O or As–O bonds which will lead to large surface recombination velocity and Fermi level pinning. Thus proper surface passivation is essential for the realization of high performance stable GaAs MOS devices. Hence to eliminate the native oxide formation and to unpin the Fermi level, in this work, an ultra-thin GaP layer was grown on GaAs. If we consider InAs QDs (electron affinity of 4.9 eV) for the purpose, it is found that InAs/ZrO₂ interface offers a barrier height of about 3.26 eV. In this work, we have thus introduced InAs QDs along with high-k dielectric (ZrO₂) to obtain GaAs MOS based memory structures to engineer the band offsets. Due to small energy bandgap and small carrier effective mass, there exists well splitted energy levels in InAs QDs, which favors multibit data storage.³² In this paper, we, thus, report the catalyst-free size controlled growth and characterization of InAs QDs on high-k dielectric (ZrO₂) layers to explore its capability of charge storage while using it in a GaAs MOS based memory device.

2 Experimental

p-Type (100) GaAs substrates, having carrier concentration of 1 × 10¹⁶ cm⁻³, were chemically surface treated by boiling sequentially with acetone and methanol followed by rinsing repeatedly in deionized water (18.2 MΩ). Then the substrates were dipped into the etchant solution of H₂O₂–NH₄OH–H₂O (1 : 1 : 2 by volume) in order to remove native oxide and elemental As. Finally those were rinsed for 3 min in deionized water and dried by N₂ gun. An ultra-thin interface passivation layer (IPL) of GaP of thickness 1.6 ± 0.3 nm was grown on p-GaAs at 540 °C by metal organic chemical vapor deposition (MOCVD) technique. Tri-methyl gallium (TMGa) and phosphine (PH₃), with a flow rate of 6.8 sccm and 70 sccm, respectively, were used as the precursors for Ga and P, respectively, whereas high purity H₂ was used as carrier gas. Then ZrO₂ (5 nm thick) was grown on it as a tunneling layer. Zirconium t-butoxide [Zr-(OC₄H₉)₄] and O₂ were used as the zirconia and oxide precursors, respectively. Here the growth was performed at 300 °C and N₂ was used as the carrier gas. The grown ZrO₂ film was annealed at 500 °C for 5 min in N₂ ambient. The growth of InAs QDs with different sizes on tunneling ZrO₂ was carried out for 2 min by MOCVD technique at different temperatures as shown in Table 1. Tri-methyl indium (TMI) and arsine (AsH₃) were utilized as the precursors for In and As, respectively. The flow rate of TMI and AsH₃ were taken as 45 and 75 sccm, respectively. Finally ZrO₂ control layer of thickness 25 nm was deposited. Top gate electrode of Al covering an area 1.96 × 10⁻³ cm² was formed by thermal evaporation. Similarly a low resistance ohmic contact was made with Pd–Ag onto the back surface of GaAs. It was then annealed at 300 °C for 3 min in argon ambience. The thickness of the deposited layers was determined by an ellipsometer (Accurion Nanofilm EP3 Model). Atomic force microscopy (AFM) (model 5100, Agilent Technologies) was used to determine the size and density of QDs grown on tunneling layer. The QDs were also characterized by high resolution transmission electron microscope (HRTEM, Jeol Jem-2100) and TEM (FEI-Tecnai G220S-Twin). The chemical analysis of the QDs was made by X-ray photoelectron spectroscopy (XPS) using PHI 5000 VersaProbeII (ULVAC-PHI, INC, Japan) system attached with a microfocused (100 μm, 25 W, 15 kV) monochromatic Al Kα source (hν = 1486.6 eV), a hemispherical analyzer, and a multichannel detector. The vacuum was maintained at ∼10⁻¹¹ torr inside the chamber throughout the experiment. To neutralize the charge, a combination of low energy Ar⁺ ions and electrons were used during the analysis. Charge calibration of the binding energy scale was done by C 1s peak at 284.6 eV. The electrical measurements of the memory devices were carried out using Keithley (4200-SCS) semiconductor parameter analyzer.

Table 1 InAs QDs with different sizes and densities at different growth temperature using MOCVD technique

Sample	QDs diameter (nm)		QDs density (cm^−2)	Growth temperature (°C)
	AFM	TEM
A	5	4	2.00 × 10^11	500
B	12.5	12	1.68 × 10^11	550
C	16	15	1.00 × 10^11	580

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3 Results and discussion

3.1. Characterizations of InAs QDs

The AFM images of InAs QDs which is homogeneously distributed over the surface of high-k corresponding to the samples A, B, and C are shown in Fig. 1(a)–(c), respectively. With the help of WSxM software, relevant parameters of the grown QDs are determined and presented in Table 1. Fig. 2(a)–(c) represent the plan-view bright field TEM micrograph of the quantum dots with approximately round in shape and the average dot diameter was found to be 4, 12, and 15 nm, respectively. The obtained values of the dot diameter from the TEM image were found to be smaller than the AFM images. This can be attributed to the tip size convolution. As the AFM tip cannot penetrate the region between two closely spaced QDs, so the size of the QDs was found to be higher than the value obtained from TEM images. Because of the enhanced migration length and increased adsorption with increasing temperature, indium (In) adatoms become more mobile and hence promote rapid nucleation. Thus the size and density of the QDs changes with increasing growth temperature. The chemical nature of InAs QDs and ZrO₂ was analyzed by high resolution XPS measurements. As depicted in Fig. 3(a), two distinct peaks of In 3d spectrum of the InAs QDs are observed.

Fig. 1 AFM images of MOCVD grown InAs QDs on tunneling ZrO₂ at a substrate temperature of (a) 500 °C, (b) 550 °C and (c) 580 °C.

Fig. 2 TEM images of the MOCVD grown InAs QDs on tunneling ZrO₂ at (a) 500 °C (b) 550 °C and (c) 580 °C substrate temperatures.

Fig. 3 X-ray photoelectron spectra of (a) In 3d and (b) the As 3d region of InAs QDs.

The one located at 443.80 eV belongs to In 3d_5/2, while the other at 451.40 eV corresponds to In 3d_3/2. Thus the value of spin orbital splitting (SOS) was found to be 7.60 eV. Fig. 3(b) shows the signature of two peaks of As. The peak at 41.40 eV is related to As whereas that at 44.40 eV denotes the oxidized As. The As peak was found to be more stronger than that obtained from the oxidized species. The spectrum of Zr 3d signal of ZrO₂ films is shown in Fig. 4(a). Two peaks of Zr 3d signal corresponding to Zr 3d_5/2 and Zr 3d_3/2 are located at 182.80 eV and 185.10 eV. The SOS value was found to be 2.3 eV which assured the fully oxidation state of Zr (Zr⁺⁴).³³ The presence of O 1s core level spectrum at 532.15 eV as shown in Fig. 4(b) again confirms the formation of ZrO₂ film.

Fig. 4 X-ray photoelectron spectra of (a) Zr 3d and (b) O 1s. The annealing of the grown ZrO₂ film was done at 500 °C for 5 min in N₂ ambient.

3.2. QDs as charge storage nodes

The MOCVD grown InAs QDs are used as charge storage elements in a GaAs MOS based memory device. Fig. 5(a) and (b) shows the schematic view of a typical GaAs MOS based non-volatile memory device with InAs QDs embedded between the high-k control and tunneling ZrO₂ dielectric layers and cross-sectional TEM image of the device, respectively. The HRTEM images of the InAs QDs on the high-k dielectric and the presence of native oxide layer on the surface of InAs QDs are shown in Fig. 5(c) and (d), respectively. The charge storage behavior was studied at room temperature through high-frequency (1 MHz) capacitance–voltage characteristics (C–V) at a gate sweeping voltage of ±10 V. As shown in Fig. 6, memory windows of width 6.81, 4.32, and 3.89 V were observed in the memory cells using QD samples A, B, and C, respectively. The hysteresis width of the memory device is found to decrease with increase in dot size. Due to profound change in density of states in QDs, the density of stored charge (D_charge) increases with decrease in dot size (d_QD) and which follows from the following relations:and

Memory window ∝ D_charge (2)

Fig. 5 (a) A schematic of the device structure and (b) cross-sectional TEM image of InAs QDs embedded in a matrix of ZrO₂. HRTEM images of the (c) InAs QDs and (d) native oxide layer on the surface of InAs QDs.

Fig. 6 Room temperature high-frequency (1 MHz) capacitance–voltage characteristics of the GaAs NVM devices containing InAs QDs with sizes 5, 12.5, and 16 nm corresponding to the growth temperature 500, 550, and 580 °C, respectively.

Moreover gradual increase in surface potential with decreasing dot size at a particular gate voltage will also lead to increase in stored charge density. For smaller dots, the generation of strongly localized trap levels becomes significant which in turn will increase the stored charge density into the QDs. However, the hysteresis in C–V characteristics can be obtained either due to the injection of charges into the trap sites of the InAs QDs or due to the presence of interface states. Again the counter clockwise hysteresis direction suggests that the carrier transport between InAs QDs and p-type GaAs substrate is due to tunneling.²⁶ To ensure that the origin of charge storage is the QDs, we have characterized our memory devices by frequency dependent C–V measurements. No frequency dispersion in accumulation capacitance is found and nearly constant hysteresis width was observed as shown in Fig. 7(a)–(c), for the memory cells made of QD samples A, B, and C, respectively, when the frequency was varied from 50 kHz to 1 MHz at ±10 V. This confirms that the hysteresis found in the C–V characteristics is due the presence of QDs and not due to the generation of trap charges in ZrO₂ or ZrO₂/GaAs interface. The maximum capacitance at the leftmost voltage (most negative) is the accumulation capacitance (C_ac), i.e. oxide capacitance (C_ox) as shown in Fig. 7(a)–(c). The capacitance per unit area of the MOS capacitor under accumulation region is the oxide capacitance which can be expressed as:

where k is the permittivity, ε₀ is the free space permittivity and t_ox is the gate dielectric thickness. The thickness (t_ox) of the high-k dielectric layer (ZrO₂ in our case) is kept constant in all the devices containing three different sizes QDs. As the MOCVD grown InAs QDs are embedded (not incorporated) between the high-k oxide layers, so there is no change in the stoichiometry of the oxide. Hence the material property, i.e. the dielectric permittivity (k) is not changed. As a result maximum capacitance, i.e. accumulation capacitance is found to be almost same in all the devices. It depends only on the applied voltage irrespective of QDs size and frequency. However the slight variation in the oxide capacitance, as shown in Fig. 7(a)–(c) is due to the change in effective oxide thickness. On the other hand, the QDs act as charge storage elements which are responsible only for the shift in flatband voltage, i.e. memory window during voltage sweeping. Thus change in the size of InAs QDs has lead to change in the flatband voltage or in other words to change the memory window. The programming (writing) and erasing operation were explained in terms of band diagram as shown in Fig. 8(a) and (b), respectively. The programming, i.e. writing operation is achieved during the application of positive voltage at the gate electrode. In this condition the inversion electrons of the GaAs side will tunnel from the GaAs conduction band to the InAs QDs. The injected electrons are then stored into the deep trap sites of InAs QDs leading to the writing operations. Again further movement of electrons towards the metal gate electrode is inhibited due to the thick control high-k dielectric layer. However during erasing operation the trapped electrons are emitted back to the GaAs on applying negative voltage to the gate electrode. The injection of holes from GaAs to InAs QDs becomes significant under erasing condition leading to large hole current. During erase cycle the electron current from the gate electrode was minimized by using high-k dielectric (ZrO₂) which acts as a blocking layer. However the back tunneling current (the current dominated by holes under programming mode and the current promoted by electrons under erasing mode) can be suppressed by using ZrO₂ as a blocking oxide layer, which exhibits large barrier height along with large relative permittivity.

Fig. 7 Room temperature frequency dependent capacitance–voltage characteristics of the GaAs MOS based NVM devices containing InAs QDs with sizes (a) 5 nm, (b) 12.5 nm, and (c) 16 nm with sweeping gate voltage ±10 V. No frequency dispersion was found in the InAs QDs embedded memory devices. This ensures the obtained memory effect is due to the charge storage in the InAs QDs.

Fig. 8 Schematic energy band diagram of Al/ZrO₂/InAs QDs/ZrO₂/(GaP)p-GaAs memory structure at (a) positive programming bias condition, and (b) negative bias for erasing modes.

The charge storage behavior of the device was investigated in terms of discharging mechanism of the charges in the InAs QDs and thus the capacitance decay was determined. From Fig. 9, the retention of the stored charge was found to be better with QD samples C. With increase in the size of the QDs, the conduction band shifts towards the lower energy compared to its bulk counterpart resulting in increase in the conduction band offset between QDs and the surrounding oxide according to the following relation^6,34,35 assuming spherical InAs QDs of diameter d in nm:

Fig. 9 Charge retention characteristics of the GaAs MOS based NVM devices of samples A, B, and C.

Hence the emission of existing stored charge carriers, i.e. back tunneling current from QDs to the substrate is suppressed. As a result the capacitance decay is reduced. Therefore the charge retention into the QDs is enhanced with increase in the size of the QDs. As shown in Fig. 9, there exist two capacitance decay regions, viz. initial fast decay and then slow decay region. Lateral charge spreading and Coulomb repulsion is responsible for the initial fast charge loss in the device while slow decay is caused due to the charge leakage through the tunnel layer. Since high growth temperature promotes the localization of QDs, initial decay is slightly minimized with increasing the size of QDs. However it was also seen that the leakage through tunneling was significantly reduced for the devices consists of QDs with bigger sizes which were grown at higher temperature leading to less generation of interface trap states.

4 Conclusion

We have successfully achieved the size controlled growth of InAs QDs by MOCVD technique on high-k ZrO₂, which is deposited onto the ultra-thin GaP passivated p-GaAs (100) substrates. From AFM and TEM images it was found that the average size of the QDs increases whereas its density decreases with increase in growth temperature. We have systematically studied the effect of the size of InAs QDs on the charge storage characteristics in GaAs MOS based non-volatile flash memory devices. Superior memory window was obtained when the size of QDs is 5 nm, whereas the charge retention is found to be enhanced with increase in QDs size on increasing growth temperature. Thus a trade-off in size of the QDs is required for an optimum memory operation.

Acknowledgements

One of the authors (SMI) acknowledges financial support from University Grants Commission, New Delhi through Maulana Azad National Fellowship for Minority Students. The authors are also thankful to Prof. Rabibrata Mukherjee, Department of Chemical Engineering, IIT Kharagpur for AFM measurements.

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