Modification of a polymer gate insulator by zirconium oxide doping for low temperature, high performance indium zinc oxide transistors

Abstract

Indium zinc oxide (IZO) thin film transistors (TFTs) with poly(4-vinylphenol-co-methylmethacrylate) (PVP-co-PMMA) gate insulators were fabricated at a low temperature (250 °C). The bottom gate IZO TFTs with a PVP-co-PMMA gate electric film exhibited inferior device performance to the top gate IZO TFTs, which was attributed to sputtering damage of the underlying polymer gate dielectric film during IZO channel formation. The charge carrier transport and interface properties of the IZO TFTs could be further improved by introducing a ZrO₂ precursor to the polymer gate insulator. The ZrO₂ molecules were well dispersed in the polymer film. The resulting hybrid dielectric film showed a higher capacitance and a smoother morphology than the PVP-co-PMMA dielectric film. The hybrid dielectric-gated IZO TFT had a high mobility of 28.4 cm² V⁻¹ s⁻¹, low subthreshold gate swing of 0.70 V per decade, and a high I_on/off ratio of 4.0 × 10⁷.

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1. Introduction

Metal oxide thin film transistors (TFTs) have attracted considerable attention as a switching device for bendable, foldable and/or transparent information displays because of their high mobility, good transparency to visible light and low temperature capability compared to amorphous Si TFTs.^1,2 To use plastic substrates as flexible displays, all the processes including deposition and thermal annealing should be performed at temperatures <250 °C to avoid deformation or warping of the plastic substrate itself.^3–6 In the case of metal oxide semiconductors, a plastic-compatible metal oxide channel layer with high mobility can be prepared because the electronic structure of amorphous or nano-crystalline metal oxides is weakly modified at a low temperature.^1,7–9 In addition, the different routes to preparation of the solution processed oxide semiconductor at a low temperature have been proposed including hydrolysis synthesis,¹⁰ combustion process,¹¹ photochemical activation,¹² alkali metal doping,¹³ and high pressure annealing.¹⁴ Conversely, a high-quality gate dielectric film, such as SiO₂, needs to be deposited at a high temperatures (>300 °C) using expensive vacuum-based plasma-enhanced chemical vapor deposition PECVD equipment.¹⁵ Recently, soluble processed gate dielectric films including Al₂O₃,¹⁶ Y₂O₃,¹⁷ HfO₂,¹⁸ and ZrO₂ ^19–21 have been studied extensively for low-cost fabrication. Although metal oxide TFTs with a soluble processed gate dielectric have achieved acceptable performance, a high annealing temperature (>300 °C)^16–21 is still needed to provide a reasonable gate leakage current and low off-state drain current.

To fully utilize the functionality of flexible displays, they need to bend or fold with a small radius (<1 mm). A mechanical failure could occur at the blanket film, such as the gate insulator rather than the isolated film, i.e., the channel and electrode region. Therefore, a polymer organic film is quite desirable as a gate dielectric for metal oxide TFTs because of its mechanical reliability. Most gate dielectric films are based on brittle inorganic materials. Although there are several reports on the fabrication of polymer-gated metal oxide TFTs,^22–26 device performance has been unsatisfactory in terms of their mobility (approximately 0.002–0.97 cm² V⁻¹ s⁻¹) and I_on/off ratio (approximately 10³ to 2 × 10⁶) because of the chemical mismatch between the metal oxide channel and the organic dielectric material. Recently, the sol–gel derived organic–inorganic hybrid dielectric has been used as a gate insulator for metal oxide TFTs, where the capacitive coupling was enhanced by the incorporation of high-k inorganic materials. Although the high capacitance and reasonable gate leakage characteristics have been achieved,^27–29 the field-effect mobilities (approximately 0.3–3.5 cm² V⁻¹ s⁻¹) for these metal oxide TFTs are still limited because of the imperfect interface, defective semiconducting oxide and/or inappropriate device architecture.

In this study, a solution-processable polymer film was used as a gate insulator for metal oxide TFTs. High-quality amorphous indium zinc oxide (IZO) without any grain boundary defect was adopted as a semiconducting channel layer to enhance the carrier transporting properties of the resulting field-effect device. The maximum processing temperature of the plastic compatible-flexible applications was less than 250 °C. The effect of the device structure on the performance of the IZO TFTs was examined. The top gate IZO TFTs exhibited a better performance compared to the bottom gate IZO TFTs, which was attributed to the prevention of sputtering damage during channel preparation. To improve the device performance substantially, the ZrO₂ precursor for the higher capacitance and better interface matching between the IZO channel and polymer dielectric film was dispersed in the PVP-co-PMMA dielectric film. These combinations including the use of an IZO channel, a high-k ZrO₂ incorporated hybrid dielectric and a top gate structure resulted in a high mobility of 28.4 cm² V⁻¹ s⁻¹ and a good I_on/off ratio of 4.0 × 10⁷.

2. Experimental

The polymer solution was prepared by dissolving PVP-co-PMMA (2 g, 1.15 mol) and poly(melamine-co-formaldehyde)methylated (0.6 g, 0.18 mol) in 7.9 mL of 2-methoxyethanol. Poly(melamine-co-formaldehyde)methylated was used as the thermal cross-linking agent. An inorganic precursor solution for ZrO₂ was synthesized using a sol–gel process with ZrCl₄, HNO₃ and H₂O dissolved in 2-methoxyethanol. The concentration of the metal precursor was 0.1 M and the ZrCl₄–HNO₃–H₂O molar ratio was 1 : 10 : 10. The two solutions of PVP-co-PMMA and zirconium chloride were blended at a volumetric ratio (PVP-co-PMMA solution/zirconium chloride solution, vol%) of 23/77. The solution for PVP-co-PMMA only film was prepared by mixing PVP-co-PMMA (1 g, 0.5 mol) and PMF (0.9 g, 0.25 mol) in 8.5 mL of 2-methoxyethanol.

The solutions were purified through a 1 μm polytetrafluoroethylene filter. The prepared polymer and hybrid polymer solutions were spin-coated onto a heavily doped silicon substrate at 3000 rpm for 30 s. The spin-coated films were annealed at 250 °C for 1 h in an air ambient furnace. To fabricate the bottom gate IZO TFTs, an IZO channel layer was deposited on the polymer insulator/heavy-doped Si substrate by DC magnetron sputtering. A 3-inch diameter In₂O₃–ZnO ceramic target was used as the IZO precursor, and the substrate-to-target distance was approximately 16 cm. During channel deposition, the dc power to the IZO target was fixed at 100 W. The working pressure was 0.4 Pa, and the relative oxygen flow rate of O₂/[Ar + O₂] was 0.3. The IZO thickness was approximately 48 nm and the In–Zn ratio was 0.5 : 0.5. The indium thin oxide (ITO) source/drain (S/D) electrode was deposited using the same sputtering system. During the deposition of the S/D electrode, the working pressure was 5 mTorr under an Ar atmosphere, and the dc power to the ITO target was 50 W. The channel width and length of the IZO TFTs were 100 μm and 150 μm, respectively. The channel and S/D electrodes were patterned through a shadow mask during deposition. The ITO S/D electrode was deposited selectively through a shadow mask onto a 100 nm thick SiO₂/Si substrate for the top gate IZO TFTs, which was followed by the formation of an IZO channel using the sputtering system. Identical polymer films were formed on the IZO/ITO/SiO₂/Si substrate. Finally, the ITO gate electrode was deposited on the polymer film. The schematic cross-sections of the IZO TFTs with a bottom gate and top gate structure were depicted in Fig. S1(a) and (b) (ESI†), respectively. The fabricated TFTs were subjected to thermal annealing at 250 °C for 1 h.

The surface morphology and the roughness of the gate insulator films were characterized by atomic force microscopy (AFM, JEOL, JSPM-5200) in the tapping mode. The depth profile of the various chemical components in the polymer gate insulator was analyzed by SIMS (ION-TOF, TOF.SIMS 5). The chemical and structural properties of the polymer-based dielectric films were characterized by transmission electron microscopy (TEM, JEOL, JEM-ARM200F), energy dispersive X-ray spectroscopy (EDS, Bruker, QUANTAX) and X-ray photoelectron spectroscopy (XPS, SIGMA PROBE, ThermoG, U.K.) analysis. The electrical properties of the channel layers were obtained using a Keithley 4200 semiconductor characterization system at room temperature in air. The C–V measurements (HP 4284A, Agilent Technologies) were also taken on the metal-oxide semiconductor capacitor sample, where an ITO electrode (400 μm in diameter) was deposited on the polymer insulator-coated Si substrate by dc magnetron sputtering.

3. Results and discussion

Fig. 1(a) shows the electric field (E)-dependent leakage current density (J) of the PVP-co-PMMA capacitor devices. The physical thicknesses of PVP-co-PMMA and hybrid PVP-co-PMMA films were approximately 226 and 223 nm, respectively, as shown in Fig. 1(c) and (d). The J values for both capacitors were plotted as a function of the thickness-normalized electric field to obtain a better comparison of results. Below 1 MV cm⁻¹, small J values (<2 × 10⁻⁷ A cm⁻²) were observed for the PVP-co-PMMA capacitor device. The ZrO₂-doped hybrid capacitor device also showed a similar leakage current characteristics below 1 MV cm⁻¹, which was approximately two orders of magnitude lower (approximately 4 × 10⁻⁵ ∼ 8 × 10⁻⁵ A cm⁻²) compared to reported polymer insulator-based capacitors.^20,21 The effective E value applied to the gate insulator was lower than 1 MV cm⁻¹ for the practical pixel switching transistor. Therefore, the ZrO₂-doped nano-composite polymer insulator exhibited reasonable gate leakage characteristics. The hybrid polymer capacitor device showed a higher critical E-field strength (approximately 3.5 MV cm⁻¹) compared to the PVP-co-PMMA capacitor device (approximately 3.0 MV cm⁻¹), which was higher than values of previously reported studies (approximately 1.5–2 MV cm⁻¹).^27,30 Fig. 1(b) shows variations of the capacitance as a function of the applied frequency. The relative dielectric constants (K) of the PVP-co-PMMA and hybrid PVP-co-PMMA layers were 3.9 and 5.6, respectively. The higher K value for the hybrid PVP-co-PMMA dielectric could be caused by the effective medium effect³¹ as a result of the incorporation of ZrO₂ molecules with high polarizability in the polymer network; this was confirmed by the depth profile of the various components of the hybrid PVP-co-PMMA dielectric layer. The structural and chemical properties of the polymer and hybrid dielectric films were characterized by TEM, EDS and XPS analysis. First, the microstructure of the hybrid PVP-co-PMMA film was characterized by TEM. The diffuse hallow pattern in the inset of Fig. 2(a) indicates the amorphous phase nature of the hybrid polymer film. The cross-sectional TEM image suggested that the homogeneous hybrid film can be obtained without any inclusion of segregate or agglomeration in the polymer matrix as shown in Fig. 2(a) and (b). The EDS analysis was performed to confirm the homogeneous dispersion of ZrO₂ in the polymer film using the EDS analyzer installed in the HRTEM equipment. The EDS spectrum for the hybrid PVP-co-PMMA film showed that the film was composed of C, O and Zr (Fig. 2(c)). The spatial composition mapping of the Zr and O elements indicated that the incorporated Zr and O atoms were uniformly distributed throughout the hybrid polymer film (Fig. 2 (d)).

Fig. 1 (a) Electric field (E)-dependent leakage current density (J) and (b) frequency-dependent capacitance of the PVP-co-PMMA and hybrid PVP-co-PMMA capacitor devices. Cross-sectional SEM images of the (c) PVP-co-PMMA and (d) hybrid PVP-co-PMMA.

Fig. 2 (a) Plain-view and (b) cross-sectional TEM images of a hybrid PVP-co-PMMA film. (c) EDS data of a hybrid PVP-co-PMMA film and (d) the elemental area mapping of C, O and Zr atoms with a scan area of 80 × 80 nm².

Fig. 3(a) shows the XPS survey spectra for the PVP-co-PMMA and hybrid PVP-co-PMMA films. The C 1s peak for the C–C bonds was assigned to calibrate the photoelectron binding energy. While the carbon, oxygen and nitrogen peaks were observed for the PVP-co-PMMA film, the hybrid film exhibited additional Zr ion-related peaks, such as Zr 3p and Zr 3d (also see Table 1). The O 1s XPS spectra for the PVP-co-PMMA and hybrid PVP-co-PMMA films are also shown in Fig. 3(c) and (d), respectively. The O 1s peak of the PVP-co-PMMA film can be de-convoluted into two bases at 531.6 and 532.9 eV. The O 1s peak centered at 531.6 eV was assigned to O–H or O=C. The higher peak at 532.9 eV can be assigned to O–C.³² In contrast, a different oxygen chemical state was observed for the hybrid PVP-co-PMMA film, as shown in Fig. 3(d). The O 1s peak of the hybrid film could be de-convoluted into three bases at 530.3, 531.6 and 532.9 eV. The peak at 530.3 eV corresponded to the ionic bonding of oxygen and zirconium (O–Zr), suggesting the formation of a ZrO₂ molecule in the hybrid polymer film; it can be further confirmed by the Zr 3d peak shown in Fig. 3(b). No metallic peak in the Zr 3d spectra was detected in the hybrid film. The Zr 3d_3/2 and 3d_5/2 peaks appeared at 182.4 eV and 182.4 eV, respectively, suggesting that the Zr–O bond has an ionic character.³³ Fig. 4(a) shows the SIMS depth profile in the hybrid PVP-co-PMMA dielectric film on the bare Si substrate. A significant zirconium and oxygen concentration was clearly observed in the entire polymer film. In addition, the ZrO₂ molecule was incorporated in the polymer film, which was consistent with our observation (TEM and XPS). Fig. 4(b) shows the spatial mapping result of the ZrO₂ molecule in the bulk region of the PVP-co-PMMA dielectric film. The uniform distribution of the ZrO₂ molecules suggested that the hydrocarbon network was formed by condensation of the zirconia gel and cross-linking reagents. The surface topographical characteristics of the PVP-co-PMMA and hybrid PVP-co-PMMA films were analyzed by AFM. The AFM topography of the PVP-co-PMMA (Fig. 5(a)) and hybrid PVP-co-PMMA (Fig. 5(b)) films shows that the hybrid polymer film had homogeneous smooth textures without local aggregation. The hybrid PVP-co-PMMA film had a small root-mean square (rms) surface roughness of 0.29 nm, which was lower than the PVP-co-PMMA film (0.32 nm). The lower rms value of the hybrid dielectric film suggested that the cross-linking between the PMMA-co-PVP and zirconia gel was moderate and homogeneous.

Fig. 3 XPS survey scans of spin-coated (a) PVP-co-PMMA and hybrid PVP-co-PMMA films. (b) A Zr 3d XPS spectrum of hybrid PVP-co-PMMA film. O 1s XPS spectra of (c) PVP-co-PMMA and (d) hybrid PVP-co-PMMA films. The fitting ratios of Lorentzian and Gaussian were fixed to 20 : 80. In addition, the gray line denotes the fitting line.

Fig. 4 (a) SIMS depth profile in the composite polymer film on the bare Si substrate. (b) Spatial mapping result of the ZrO₂ molecule in the bulk region of the hybrid polymer film. The thickness of the composite film was approximately 230 nm.

Fig. 5 AFM images of the (a) PVP-co-PMMA and (b) hybrid PVP-co-PMMA polymer films.

Table 1 Comparisons of C 1s, Zr 3d and de-convoluted O 1s peaks from XPS spectra of the PVP-co-PMMA and hybrid PVP-co-PMMA films

	C 1s	O 1s			Zr 3d
		C–O	C=O, O–H	Zr–O	3d5/2	3d3/2
PVP-co-PMMA	284.4 eV	532.9 eV (50.5%)	531.6 eV (49.5%)	—	—	—
Hybrid PVP-co-PMMA	284.3 eV	532.9 eV (28.4%)	531.6 eV (53.0%)	530.3 eV (18.6%)	182.2 eV	184.6 eV

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IZO TFTs with two types of architectures were fabricated. Fig. 6(a) and (b) shows the representative transfer characteristics of the IZO TFTs with the bottom gate and top gate structure, respectively. The field-effect mobility (μ_FE) was determined from the incremental slope of the I_DS^1/2 vs. V_GS plot in the saturation region using the following equation:

I_DS = (WC_i/2L)μ_FE(V_GS – V_th)²V_DS, (1)

where L is the channel length, W is the width, and C_i is the gate capacitance per unit area. V_th is defined as the gate voltage that induces a drain current of 1 nA at V_DS = 5.1 V. The subthreshold gate swing (SS = dV_GS/d log I_DS [V per decade]) was extracted from the linear part of the log(I_DS) vs. V_GS plot.

Fig. 6 Representative transfer characteristics of the IZO TFTs with the (a) bottom gate and (b) top gate structures. Output characteristics of the IZO TFTs with the (c) bottom gate and (d) top gate structures.

The bottom gate IZO TFTs with a PVP-co-PMMA dielectric film showed only a marginal performance. The μ_FE, SS, V_th and I_on/off ratios were 9.0 cm² V⁻¹ s⁻¹, 5.0 V per decade, −12.5 V, and 2 × 10⁵, respectively. The output characteristic of the IZO TFTs with a PVP-co-PMMA dielectric film is shown in Fig. 6(c). However, the top gate IZO TFTs exhibited better performance. Although the μ_FE value (8.5 cm² V⁻¹ s⁻¹) of the top gate devices was comparable to the bottom gate devices, their SS, V_th and I_on/off ratio were improved substantially to 2.0 V per decade, −10.0 V and 1.0 × 10⁷, respectively. The more negative V_th value and the higher off-state I_DS (I_off) of the bottom gate devices could be explained by the energetic ion bombardment effect. The underlying polymer gate dielectric film of the bottom gate device was likely affected by adverse sputtering damage during channel deposition. The in-diffusion of energetic In and Zn cations to the polymer dielectric during channel deposition was the origin of the higher electron density of the metal oxide channel region. Therefore, the negative V_th and high I_off values of the IZO TFTs can induce opposite electron carriers in the active layer because of the positive cations that migrated in the polymer insulator.²² The similar energetic bombardment-induced damage during sputtering process of the transparent conducting oxide films such as IZO or ITO has been reported to adversely affect the underlying organic film and degrade the electrical properties of the resulting organic light-emitting diodes.^34–37 IZO TFTs with only a ZrO₂ film were also fabricated for comparison. The solution-processable ZrO₂ film prepared at 250 °C was so thin (approximately 15 nm) that the resulting IZO TFTs exhibited a simple conducting behavior due to the unacceptably high gate leakage current. This high leakage current was not improved by the multiple coating of the ZrO₂ film.

The SS value of a given TFT device is related to the total density of traps including the bulk (N_SS) and semiconductor–insulator interfacial traps (D_it) according to the following equation:³⁸

where q is the electron charge, k_B is Boltzmann's constant, T is the absolute temperature, and t_ch is the channel layer thickness. The N_SS and D_it values in the IZO TFTs were calculated by setting one of the parameters to zero. In this study, the N_SS and D_it values corresponded to the maximum trap density formed in a given system. The D_it,max values for the bottom gate and top gate IZO TFTs were 6.4 × 10¹² and 2.6 × 10¹² cm⁻² eV⁻¹, respectively (see Table 2). The high D_it,max value for the bottom gate device can also be explained by the energetic ion bombardment effect. In addition to cation in-diffusion, the energetic particles, such as high energy electron and charged ions during sputtering process, attacked the surface of the organic films and transferred their high energies,^37,39 which caused defect states and led to a higher D_it,max and gate leakage current (also see Fig. 6). The detrimental sputtering damage could be mitigated by reversing the stacking sequence of the gate insulator and the active channel layer. The sputtering damage to the polymer gate dielectric could be prevented because an active channel layer was formed prior to the gate dielectric coating in the top gate structure. This could explain why the top gate devices had a lower D_it,max and gate leakage current and a high I_on/off ratio. This difference between the two devices could also be confirmed by the operation gate voltage stress-induced instability. However, the bottom gate device suffered from a large hysteresis (approximately 10 V), while the top gate device exhibited only a small hysteresis (0.9 V). The superior operation stability of the top gate devices was confirmed by their lower D_it,max values. Therefore, the top gate configuration was chosen for further comparison of the IZO TFTs with the PVP-co-PMMA and hybrid dielectric films.

Table 2 Device parameters including μ_FE, SS, V_th, I_on/off, D_it,max, and N_ss,max of the IZO TFTs with a polymer gate insulator

TFT structure	Gate insulator	μFE (cm^2 V^−1 s^−1)	SS (V per decade)	Vth (V)	Ion/off	Dit,max (eV^−1 cm^−2)	Nss,max (eV^−1 cm^−3)
Bottom gate	Polymer	9.0 ± 2.5	5.0 ± 0.3	−12.5 ± 4.5	2.0 × 10^5	6.4 × 10^12	1.3 × 10^18
Top gate	Polymer	8.5 ± 1.4	2.0 ± 0.4	−10.0 ± 1.5	1.0 × 10^7	2.6 × 10^12	5.3 × 10^17
Top gate	Composite	28.4 ± 1.5	0.7 ± 0.1	−2.0 ± 1.5	4.0 × 10^7	1.6 × 10^12	3.4 × 10^17

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Fig. 7(a) and (b) show the representative transfer and output characteristics of the IZO TFTs with a hybrid PVP-co-PMMA gate dielectric layer, respectively. A significant improvement in the device performance was observed for the hybrid dielectric-gated IZO TFTs. The μ_FE and SS values for the hybrid PVP-co-PMMA gated device were improved to values of 28.4 cm² V⁻¹ s⁻¹ and 0.70 V per decade, respectively. Moreover, the V_th value was shifted from −10.0 V to −2.0 V, and the I_on/off ratio was increased to 4.0 × 10⁷. The small hysteresis (approximately 0.6 V) and lowest D_it,max (1.6 × 10¹² cm⁻² eV⁻¹) values of the hybrid dielectric-gated IZO TFTs suggested that the interfacial properties between the IZO and ZrO₂-incorporated polymer could be improved. There are several literature reports on polymer gate insulator gated metal oxide TFTs. The fabricated devices suffer from low field-effect mobility (approximately 0.002–1.1 cm² V⁻¹ s⁻¹) and small I_on/off ratios (approximately 10³ to 2 × 10⁶),^23–27,30 which could be attributed to either a chemical/physical attack during the formation of the semiconducting oxide film or the incompatible interfacial properties between the oxide channel and the organic dielectric film. The gate dielectric films for high-quality metal oxide TFTs primarily consist of the oxide-based material. This finding suggests that the oxygen backbone structure through the channel/insulator minimizes the interfacial trap density. In this study, the continued oxygen backbone structure could be assisted with the ZrO₂ particles dispersed in the polymer layer. Although the ZrO₂ volume dependent interfacial property was not optimized, the combined approach with a hybrid PVP-co-PMMA gate insulator and top gate architecture could be desirable for the truly malleable applications of metal oxide TFTs.

Fig. 7 Representative (a) transfer and (b) output characteristics of the IZO TFTs with a hybrid PVP-co-PMMA gate dielectric layer.

4. Conclusion

This study examined the effects of the device architecture on the polymer gated IZO TFTs. The device architecture played an important role in determining the properties of the fabricated oxide TFTs with a PVP-co-PMMA gate insulator. The top gate IZO TFTs exhibited a reasonable μ_FE, SS, V_th, and good I_on/off ratio of 8.5 cm² V⁻¹ s⁻¹, 2.0 V per decade, −10.0 V, and 1.0 × 10⁷, respectively, whereas the bottom gate IZO TFTs showed marginal performance (the μ_FE, SS, and I_on/off ratio were 9.0 cm² V⁻¹ s⁻¹, 5.0 V per decade, −12.5 V and 2 × 10⁵, respectively). The inferior performance of the bottom gate device was attributed to the energetic ion bombardment effect in the polymer gate dielectric layer during the sputtering process. Therefore, the top gate structure was desirable for sputtered metal oxide channel-based TFTs. The device performance can be further improved by doping the hybrid PVP-co-PMMA gate dielectric film with ZrO₂. The increased capacitance, improved surface morphology and interfacial properties of the hybrid PVP-co-PMMA gate insulator resulted in high performance IZO TFTs: the μ_FE, SS, V_th and I_on/off ratio were 28.4 cm² V⁻¹ s⁻¹, 0.70 V per decade, −2.0, and 4.0 × 10⁷, respectively. Therefore, the top gate metal oxide TFTs with a high-k ZrO₂ and polymer blended gate dielectric were promising switching devices for malleable electronics.

Acknowledgements

This study was supported by the industrial strategic technology development program funded by MKE/KEIT (10041808).

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Footnote

† Electronic supplementary information (ESI) available. See DOI: 10.1039/c4ra08548e

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