Morphological impact of zinc oxide layers on the device performance in thin-film transistors

Abstract

Zinc oxide thin-films are prepared either by spin coating of an ethanolic dispersion of nanoparticles (NP, diameter 5 nm) or by spray pyrolysis of a zinc acetate dihydrate precursor. High-resolution electron microscopy studies reveal a monolayer of particles for the low temperature spin coating approach and larger crystalline domains of more than 30 nm for the spray pyrolysis technique. Thin-film transistor devices (TFTs) based on spray pyrolysis films exhibit higher electron mobilities of up to 24 cm² V⁻¹s⁻¹ compared to 0.6 cm² V⁻¹s⁻¹ for NP based TFTs. These observations were dedicated to a reduced number of grain boundaries within the transistor channel.

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Solution processing is envisioned as a key technology in low-cost production of medium-performance electronic devices on large-area and preferably flexible substrates.^1–3 To achieve a suitable device performance a balanced combination of materials, processes and device structures is necessary. The wide band gap II–VI semiconductor zinc oxide has already proven its versatility and was employed in a number of electronic devices ranging from solar cells and UV-diodes, to sensors and thin-film transistors.^4–11

The solution-based deposition (e.g. printing, dip- or spin coating) of inorganic semiconductor thin films basically follows two general approaches: (a) synthesis of nanoparticles with the desired shape and size followed by dispersion in a suitable solvent and deposition^12–14 or (b) using precursor solutions to deposit the film and subsequently applying a heat treatment to achieve the conversion to the semiconductor.¹⁵ In both cases the device performance is related to densely packed films with connected particles or lattices to carry charges over longer distances.

In this work, we compare two different solution based ZnO materials in field-effect transistors, namely spin coated nanoparticles and ZnO layers prepared by spray pyrolysis of zinc acetate. The charge transport properties related to the different thin-film morphologies will be discussed and specific advantages of each approach will be concluded.

Cross-sectioning of the device structures for transmission electron microscopy (TEM) investigation was performed by focused ion beam (FIB) milling employing a shadow-FIB technique.^16,17 For better dimensional stability of the cross-section samples the images of the nanoparticle layers were recorded on an inverted device stack. The images were taken with a Titan³ 80-300 instrument equipped with an image aberration corrector. Electrical characterization was carried out in ambient conditions using the Agilent B1500A parameter analyzer.

Zinc oxide nanoparticles (ZnO NPs) with average diameter of 5 nm¹⁸ were synthesized using zinc acetate dihydrate and lithium hydroxide in a precipitation process from alcoholic liquid phase described by Marczak et al.¹⁹ Film deposition was then carried out by spin coating (2000 rpm, 20 s) a ZnO dispersion in ethanol, followed by 6 min drying at 100 °C. This process leads to a monolayer of particles (Fig. 1), as the film thickness of about 5–6 nm corresponds directly to the particle diameter. No agglomerates are visible and the substrate is homogeneously covered.

Fig. 1 Active device layer of spin coated zinc oxide nanoparticles. Individual particles are visible in the high resolution TEM image and some of their lattice planes are highlighted with yellow lines.

The method of spray pyrolysis uses precursor solutions that are sprayed onto a heated substrate, usually in the range of 200–500 °C. With this general procedure various materials (including ZnO, TiO₂, SnO₂, CuInS₂, CdSe or Al₂O₃) can be processed into thin films with corresponding precursors.^20–27 A broad field of applications like TFTs, solar cells or phosphors could already be demonstrated by applying this technique.

For the spray pyrolysis, a 0.1 M solution of zinc acetate in methanol was manually sprayed onto the heated substrate with a conventional airbrush system in a process adapted from Bashir et al.²⁸ The substrate temperature was set to 370 °C via a supporting hotplate. Spraying time was 15 s, followed by 60 s of drying; this cycle was repeated twice. The resulting layer structure revealed by scanning transmission electron microscopy (STEM) shows a rough ZnO film (bright contrast) with a thickness of about 30 nm (Fig. 2, left). Especially the bottom and top areas contain crystallites with diameters in the range of 15 nm, while the middle part of the layer is more homogenous with larger crystal sizes. The high resolution image (Fig. 2, right) shows the presence of continuous crystalline areas that extend over more than 30 nm.

Fig. 2 Left: STEM Z-contrast image of the layer stack in setup B. Right: high resolution TEM image of the ZnO layer fabricated by spray pyrolysis. Yellow bars indicate the orientation of lattice planes and the arrows show how far they expand along the layer.

Field-effect transistors were fabricated and electrically characterized in two different bottom-gate top-contact setups (see Fig. 3a and b). Both setups use thermally oxidized silicon wafers (100 nm SiO₂) as substrates and consist of 30 nm Al gate, and Al source and drain electrodes (W/L = 15). For setup A, a 190 nm cross-linked polymer dielectric layer (poly(4-vinylphenol), PVP; ε_r = 3.6) was used.²⁹Spin coating a ZnO–NP formulation in ethanol and drying at 100 °C lead to the semiconductor layer. Due to the high deposition temperature of 370 °C during spray pyrolysis, the PVP dielectric is not suitable for spray pyrolysis ZnO devices. Therefore, in setup B, an ultrathin (5.4 nm) organic–inorganic hybrid dielectric (ε_r = 3.75) was used. The hybrid dielectric consists of 3.6 nm AlO_x created by plasma treatment of the Al gate electrode (Diener electronic plasma chamber “Pico”) and a self-assembled monolayer of C₁₄-phosphonic acid (C₁₄-PA) of 1.8 nm thickness.³⁰

Fig. 3 Schematic cross-section and corresponding transfer and output characteristics of TFTs fabricated in setup A (a, c, and e) using zinc oxide nanoparticles and in setup B (b, d, and f) with spray pyrolysis derived ZnO.

Both transistor configurations show typical n-type behavior with only a small hysteresis in forward and backward scan direction and a good saturation in the output characteristics, see Fig. 3. For all TFTs, the charge carrier mobility µ was extracted in the saturation regime using the equation I_D = W/(2L)µC_i(V_GS − V_TH)², with the drain current I_D, channel length L and width W, the gate capacitance per unit area C_i, gate–source voltage V_GS and threshold voltage V_TH.

Best devices in setup A exhibit electron mobilities up to 0.6 cm² V⁻¹s⁻¹ with a threshold voltage V_TH of 5.9 V. The on/off current ratio and I_D/I_G ratio are in the range of 10³ and 10², respectively. The values of charge carrier mobility in bottom-gate devices exceed the results of previous work with similar ZnO particles,³¹ probably due to a superior coverage of particles along the dielectric layer without a strong agglomeration.

Devices in setup B operate at significantly reduced supply voltages (V_GS = 2 V) and show a reduced threshold voltage of 1.2 V, due to the tiny hybrid dielectric layer. Along with larger crystal sizes (Fig. 2, right) compared to the ZnO NP layer, a larger drain current is observed. Increased mobilities of up to 24 cm² V⁻¹s⁻¹ and on/off ratios in the range of 10⁵ were obtained. These are comparable results to those given by the group of Anthopoulos for spray coated undoped ZnO films.^20,28 As the spray pyrolysis process was executed manually, certain device-to-device variations were a given consequence. However, it has already been shown that the process itself can be automated and even a preferred crystal orientation can be achieved by careful tuning of process parameters showing the potential to realize reliable devices.²²

Obviously, the increased charge carrier mobility in spray coated ZnO films nicely relates to extended crystalline domains in the transistor channel, leading to fewer grain boundaries compared to NP films. The spray pyrolysis derived semiconductor layer exhibits oriented lattice planes (Fig. 2, right) which are formed during the thermal conversion. In contrast, the nanoparticles show randomly oriented lattice planes within the film, even though the individual particles appear to be single crystalline and well connected.

Comparing simply the electrical performances in the TFT devices, the ZnO layers deposited by spray pyrolysis outperform those of the particle layers by one order of magnitude. However, other factors have to be taken into account when certain products and functionalities are envisioned. As spray coated ZnO films rely on thermal conversion at elevated temperatures well above 200 °C,²⁸ this eliminates the possible use of standard polymer substrates. For flexible applications, cost intensive high temperature resistant polymers like polyimid are required. Formulations of ZnO NP do not have this restriction and can thus be applied as solution processed semiconductor, e.g. on polyethylene naphthalane substrates as demonstrated in a different, top-gated setup (setup C, see ESI†). Such devices exhibit electron mobilities of up 1.4 cm² V⁻¹s⁻¹, which is only a slight reduction when opposed to devices in the same setup on rigid SiO₂ substrates (2 cm² V⁻¹s⁻¹).

Conclusions

In summary, we have compared two different solution based techniques to fabricate ZnO TFTs. Nanoparticle dispersions were processed by spin coating with a maximum thermal treatment of the semiconductor of 100 °C. Precursor solutions were deposited and converted to ZnO layers by spray pyrolysis at a temperature of 370 °C. With electron mobilites up to 24 cm² V⁻¹s⁻¹ the performance of spray pyrolysis ZnO exceeds that of the particles. The increased mobility is clearly addressed to improved crystalline arrangement in the spray coated films. However, targeting applications on standard polymers, spray pyrolysis as a deposition technique is unfavourable due to high thermal load. Related to the objective, both approaches provide excellent opportunities with promissing device parameters.

Acknowledgements

The authors are thankful for financial support by the Graduate School 1161—“Disperse Systems for Electronic applications”, and of the Cluster of Excellence “Engineering of Advanced Materials” which are both funded by Deutsche Forschungsgemeinschaft (DFG) and Evonik Degussa GmbH, Germany.

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Footnote

† Electronic supplementary information (ESI) available: Schematics and data of devices in setup C. See DOI: 10.1039/c0nr00800a

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