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Issue 5, 2015
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Scaling of pneumatic digital logic circuits

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Abstract

The scaling of integrated circuits to smaller dimensions is critical for achieving increased system complexity and speed. Digital logic circuits composed of pneumatic microfluidic components have to this point been limited to a circuit density of 2–4 gates cm−2, constraining the complexity of the digital systems that can be achieved. We explored the use of precision machining techniques to reduce the size of pneumatic valves and resistors, and to achieve more accurate and efficient placement of ports and vias. In this way, we attained an order of magnitude increase in circuit density, reaching as high as 36 gates cm−2. A 12-bit binary counter circuit composed of 96 gates was realized in an area of 360 mm2. The reduction in size also brought an order of magnitude increase in speed. The frequency of a 13-stage ring oscillator increased from 2.6 Hz to 22.1 Hz, and the maximum clock frequency of a binary counter increased from 1/3 Hz to 6 Hz.

Graphical abstract: Scaling of pneumatic digital logic circuits

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Article information


Submitted
06 Sep 2014
Accepted
29 Dec 2014
First published
06 Jan 2015

Lab Chip, 2015,15, 1360-1365
Article type
Paper
Author version available

Scaling of pneumatic digital logic circuits

P. N. Duncan, S. Ahrar and E. E. Hui, Lab Chip, 2015, 15, 1360
DOI: 10.1039/C4LC01048E

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