Two-bit memory and quantized storage phenomenon in conventional MOS structures with double-stacked Pt-NCs in an HfAlO matrix

Abstract

A two-bit memory and quantized storage phenomenon are observed at room temperature for a device based on the traditional MOS structure with double-stacked Pt-nanocrystals (Pt-NCs). A 2.68 and 1.72 V flat band voltage shift (memory window) has been obtained when applying a ±7 V programming/erasing voltage to the structures with double-stacked Pt-NCs. The memory windows of 2.40 and 1.44 V can be retained after stress for 10⁵ seconds, which correspond to 89.55% and 83.72% stored charges reserved. The quantized charge storage phenomenon characterized by current–voltage (J–V) hysteresis curves was detected at room temperature. The shrinkage of the memory window results from the decreasing tunneling probability, which strongly depends on the number of stacks. The traps, de-traps and quantum confinement effects of Pt-NCs may contribute to the improvement of dielectric characteristics and the two-bit memory behavior. The multi-bit memory and quantized storage behavior observed in the Pt-NCs stacks structure at room temperature might provide a feasible method for realizing the multi-bit storage in non-volatile flash memory devices.