Method of high-order advanced lithography overlay correction to enhance the manufacturing performance of integrated circuits

Abstract

As integrated circuit (IC) manufacturing advances toward smaller technology nodes, conventional lithography methods are increasingly challenged by the diffraction-limited resolution, escalating process complexity, and rising costs. Among these challenges, overlays have a particularly pronounced impact on manufacturing quality. To address this issue, this paper proposes a high-order overlay correction model that employs a two-dimensional fifth-order polynomial to accurately fit and characterize the distribution of overlays. The model's effectiveness is validated through finite element simulations. By incorporating an array of piezoelectric actuators, thermally induced deformation control units, and micro-mechanical clamping mechanisms, the model enables precise regulation of complex stress fields and localized temperature variations along the mask boundary, thereby enabling effective compensation of high-order overlay errors. Simulation results demonstrate that the proposed approach reduces the |mean| + 3σ of overlay to below 1 nm. It achieves nearly 100% correction for 1st-order and 2nd-order overlay components, over 80% correction for 3rd-order and 4th-order components, and a correction rate of 68.16% for 5th-order errors. Multiple randomized verification tests indicate average compensation efficiencies of 96.85% in the x-direction and 97.36% in the y-direction, highlighting the model's robustness and consistency. In practical processes, the model successfully reduces actual wafer overlay to |mean| + 3σ values of 4.22 nm and 6.26 nm in the x and y directions, respectively. This study presents an efficient and reliable solution for high-order overlay compensation in advanced lithography, offering significant benefits for enhancing IC manufacturing performance and reliability.