Performance limit of one-dimensional SbSI nanowire transistors

Abstract

It has been suggested that low-dimensional materials can substitute for silicon-based materials to get around the scaling issues in existing field-effect transistors (FETs). The current study is based on the simulation of gate-all-around (GAA) SbSI nanowire FETs by making use of the ab initio quantum transport technique. The simulated results manifest gate-length (L_g, L_g = 5, 3, 1 nm) n- and p-type GAA SbSI FETs with a suitable underlap that is able to fulfill the power dissipation, delay time, and on-state current for the 2028 prerequisites for the high-performance and low-dissipation requirements of the International Technology Roadmap for Semiconductors (ITRS) of 2013. As a result, GAA SbSI FETs may be a viable option for scaling Moore's law to 1 nm.