Device performance and strain effect of sub-5 nm monolayer InP transistors

Abstract

Indium phosphide (InP) has a higher electron mobility, electron saturation velocity, and drain current than silicon (Si), and the ultra-thin (UT) InP field-effect transistor (FET) probably possesses a better device performance than the UT Si counterpart. Recently, InP film has been successfully grown with a thickness down to 6.3 nm. In this paper, we study the device performance of the n-type sub-5 nm monolayer (ML) InP (the limitation of UT InP film) FETs based on the ab initio quantum transport simulation. The on-state current, intrinsic delay time, and power-delay product of the ML InP FETs could meet the International Technology Roadmap for Semiconductors (ITRS) demands for the high-performance/low-power devices until the gate length is reduced to 2/4 nm. In addition, we investigate the effect of strain on the ML InP FETs, but unfortunately, strain cannot significantly improve the device performance. Therefore, UT InP is a potential channel candidate for next-generation FETs.