Laminated three-dimensional carbon nanotube integrated circuits

Abstract

The fabrication procedure for each layer of the device in monolithic three-dimensional (3D) integration still follows the design philosophy of traditional planar silicon-based circuits, and such integrated circuits will ultimately be limited by the same scaling constraints that face silicon field-effect transistors. We report the direct formation of laminated 3D integrated circuits by the layer-by-layer stacking of each component through two different techniques. One is to use carbon nanotubes (CNTs) as the channels of thin-film transistors because of their low-temperature fabrication and layer-to-layer transfer capabilities. The other is to use a suitable separator between every two layers to isolate them, because the separator is not only able to maintain the stability of the performance of each component after coating, but is also a good insulator that can prevent interlayer interactions. A 5-stage CNT ring oscillator laminated onto a single inverter is finally reported, which can reduce the device area by approximately 80%, and should be greatly helpful for the continuous improvement of device functionality and integration.