Device performance limits and negative capacitance of monolayer GeSe and GeTe tunneling field effect transistors

Abstract

Exploring the device performance limits is meaningful for guiding practical device fabrication. We propose archetype tunneling field effect transistors (TFETs) with negative capacitance (NC) and use the rigorous ab initio quantum transport simulation to explore the device performance limits of the TFETs based on monolayer (ML) GeSe and GeTe along with their NC counterparts. With the ferroelectric dielectric acting as a negative capacitance material, the device performances of both the ML GeSe and GeTe NCTFETs outperform their TFET counterparts, particularly for the on-state current (I_on). I_on of the optimal ML GeSe and GeTe TFETs fulfills the demands of the International Technology Roadmap for Semiconductors (ITRS 2015 version) for low power (LP) and high performance (HP) devices, at the “6/5” node range, while with the aid of 80 nm and 50 nm thickness of ferroelectric SrBi₂Nb₂O₉, both their NC counterparts extend the fulfillments at the “4/3” node range.