An empirical study-based state space model for multilayer overlay errors in the step-scan lithography process

Abstract

In semiconductor manufacturing, the multilayer overlay lithography process is a typical multistage manufacturing process; one of the key factors that restrict the reliability and yield of integrated circuit chips is overlay error between the layers. To effectively control overlay error, an accurate error model that can present the introduction, accumulation and propagation of multilayer overlay error is indispensable. On the basis of the existing original physical model, a model for multilayer overlay error based on the state space modeling method is proposed in this study. The model can provide information on the wafer coordinates and field coordinates by a coefficient matrix. The model was applied to 810 groups of real data collected from a wafer manufacturing plant for empirical validation. The test results demonstrate that the overlay error and coordinates that are predicted by the state space model work well in tracking the variation in the actual measured values; the rates of target hitting and the R-square values of different sampling variables are very close to one.