Non-silicide Schottky barrier p-type tunnel FET with a gate-around-drain structure formed by a junctionless FET process

Abstract

Unlike conventional tunnel FETs (TFETs) that adopt a p–i–n junction structure, a junctionless channel with a non-silicide Schottky barrier source/drain was explored as a novel device structure for p-type TFETs. A circuit model consisting of two Schottky diodes was proposed to explain the device operation mechanism. With the gate-around-drain layout, the applied gate voltage can more effectively control the voltage at the channel and consequently modulate the operation mode of Schottky diodes at the source and drain. With the majority of carriers tunneling through the thin Schottky barrier, p-type TFETs enjoy a steep subthreshold swing (SS) of 35 mV dec⁻¹ over 3 orders of drain current. By biasing the drain and gate at −0.5 V, the TFETs demonstrate a competitive drive current of 2.25 μA μm⁻¹ and high ON/OFF current ratio of 1.2 × 10⁵. Furthermore, the TFETs exhibit robust reliability against high electric field stress at −10 MV cm⁻¹ for 10⁴ s. Owing to the simple structure and the capability to achieve a high drive current with a steep SS at low voltage, the proposed TFET structure paves a new avenue to implement low-power green electronics with full compatibility with an advanced gate-last process.