Improved performance of nanocrystal memory for aminosilane-mediated Au–SiO2 embedded core–shell nanoparticles

Abstract

We present a memory property study of floating gate structure embedded with Au–SiO₂ core–shell nanoparticles (NPs). Herein, the Au–SiO₂ core–shell configuration was readily fabricated by a self-assembly (SAM) layer-by-layer process using 3-aminopropyltrimethoxysilane (APTMS) as a versatile mediator. This functional APTMS served as both a binder for adsorbing colloidal Au NPs onto the substrate and to self-organize a SiO₂ ultra-thin shell to cover the Au NP cores. A two-run APTMS SAM process was employed to develop the core–shell configuration. The first-run APTMS formed a well-organized monolayer on the substrate which was responsible for the obtained uniform SAM with high density of Au NPs. Next, the second-run APTMS formed an APTMS bilayer around the Au NPs. During the SAM process, a polymerization process simultaneously occurred with the reaction of neighboring silanol groups to form an Si–O–Si network structure. The polymerization was completed by a 400 °C-annealing to form a SiO₂ layer within the APTMS bilayer. In addition, the annealing also resulted in the decomposition of the APTMS and released the preformed SiO₂ layer from the APTMS bilayer. The ultra-thin SiO₂ layer was flexible enough to cover the Au NP cores, eventually constructing the Au–SiO₂ core–shell structure. Compared to Au nanocrystal (NC) memory, Au–SiO₂ core–shell NCs show a larger memory window and significantly improved retention performance, which are attributed to the SiO₂ shell-induced superior NP/oxide interface qualities and the characteristics of the Au NPs.