Innovations of metallic contacts on semiconducting 2D transition metal dichalcogenides toward advanced 3D-structured field-effect transistors

Abstract

2D semiconductors, represented by transition metal dichalcogenides (TMDs), have the potential to be alternative channel materials for advanced 3D field-effect transistors, such as gate-all-around field-effect-transistors (GAAFETs) and complementary field-effect-transistors (C-FETs), due to their inherent atomic thinness, moderate mobility, and short scaling lengths. However, 2D semiconductors encounter several technological challenges, especially the high contact resistance issue between 2D semiconductors and metals. This review provides a comprehensive overview of the high contact resistance issue in 2D semiconductors, including its physical background and the efforts to address it, with respect to their applicability to GAAFET structures.

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1. Introduction

The electronics industry has been further developed through the miniaturization of transistors in integrated circuits, providing enhanced performance and greater energy efficiency in computing power.¹ The continuous progression toward smaller transistor size has been enabled through the introduction of innovative materials like high-k metal gate (HKMG)² and novel transistor designs such as fin field-effect transistors (FinFETs).³ Recently, gate-all-around field-effect transistors (GAAFETs) have emerged as a subsequent device architecture to FinFETs, with the potential to propel technological node advancements further (Fig. 1(a)).⁴ GAAFETs deliver enhanced performance and scalability when compared to FinFETs or conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). The structure of GAAFET involves its channel surrounded by a gate on all sides, providing improved electrostatic control, faster switching speed and lower power consumption. Furthermore, it provides advanced scalability because its channels can be stacked vertically.^4–6 This could also be applicable to the fabrication of complementary FETs (CFETs), in which n- and p-type MOSFETs are stacked on top of each other.⁷ Thus, GAAFET technology has been actively researched and developed by semiconductor manufacturers as a successor to FinFET technology.⁸

Fig. 1 (a) Schematics of a planar MOSFET with HKMG, FinFET, GAAFET, and 2D channel FET. (b) Carrier mobility versus thickness of WSe₂, MoS₂, WS₂, silicon (Si), and germanium (Ge). Filled symbols refer to electron mobilities and open symbols to hole mobilities. The mobilities of 2D semiconductors show moderate values at sub-1 nm thickness, while those of silicon and germanium drastically decrease. Reprinted from ref. 9 with permission from John Wiley and Sons. (c) Scaling length versus channel thickness of MoS₂ and Si. MoS₂ shows a smaller scaling length, indicating better immunity to short channel effects (SCEs). Reprinted from ref. 10 with permission from The American Association for the Advancement of Science. (d) Drain-induced barrier lowering (DIBL) and subthreshold swing (SS) versus gate lengths of Si channel FETs (green) and MoS channel FETs (red and blue), SS versus temperature of MoS₂ channel FETs. MoS₂ shows lower DIBL and SS. Reprinted from ref. 11 with permission from IEEE. (e) Comparison of reported contact resistance values versus various contact engineering technologies. The data are from ref. 12–71.

Further downscaling of GAAFETs toward advanced technological nodes is anticipated to accompany the thinning of their channels.^72,73 However, the utilization of silicon (Si) as a channel material for GAAFETs encounters a limitation in reducing the channel thickness to less than 5 nm, primarily because it results in substantial mobility degradation.^74,75 Consequently, researchers have initiated investigations into 2D semiconductors, represented by transition metal dichalcogenides (TMDs),⁷⁶ as a prospective substitute channel material for GAAFETs. In contrast to silicon, 2D semiconductors exhibit a reasonable carrier mobility, even if their thickness is less than 1 nm, due to their inherent atomic thinness and dangling-bond-free nature (Fig. 1(b)).⁹ They also have a notably lower dielectric constant compared to that of silicon, exhibiting a significantly reduced scaling length that indicates enhanced immunity to short-channel effects (Fig. 1(c) and (d)).^10,11

Despite the advantages offered by 2D semiconductors, integrating them into the channel region is challenging due to the stringent requirements of a stable and matured process technology compatible with logic device technology reliant on a 300 mm wafer fabrication process. The technological hurdles that 2D semiconductors face include wafer-scale single-crystalline growth and high-quality HKMG stack formation.

Notably, the presence of high contact resistance at the metal/2D semiconductor junction emerges as a significant issue. Despite the dangling-bond-free nature of 2D semiconductors, the occurrence of Fermi-level pinning (FLP) phenomena⁷⁷ at these junctions leads to a substantial injection barrier height for both electrons and holes. Moreover, there is a van der Waals (vdW) gap present between the metal and 2D semiconductors, serving as a tunnelling barrier.⁷⁸ As a result, the substantial barrier height and the vdW gap impede the injection of carriers from the metal to 2D semiconductors and vice versa. This results in elevated contact resistance, typically ranging from a few to several tens of kΩ μm for multilayer 2D semiconductors. The contact resistance in monolayer 2D semiconductors experiences an increase due to their larger bandgap when compared to their bulk counterparts,⁷⁶ reaching values up to several hundreds of kΩ μm.⁷⁹ Furthermore, addressing the challenge of high contact resistance becomes even more formidable in advanced technological nodes, where contacts must be established in intricate and limited 3D spaces. This limitation can constrain choices for contact engineering strategies. The elevated contact resistance begins to impede the on-current, even in relatively long-channel 2D FETs (L_CH = 1 μm).⁸⁰ Scaled 2D channel FETs with reduced channel lengths (L_CH < 1 μm) typically exhibit an on-current in the range of a few hundred μA μm⁻¹ without the application of contact engineering technologies,^81,82 which needs to be improved to meet the range of 532–753 μA μm⁻¹ required for future technology nodes.⁸³ Achieving this range is imperative for ensuring the circuit-level performance of 2D channel FETs and facilitating their integration into the electronics industry.

Therefore, with high interest, many researchers have been steadily conducting research to address the high contact resistance issue and such efforts led to successful reports of high currents above 1000 μA μm⁻¹.^12,13 However, although 2D channel GAAFETs,^84,85 CFETs⁸⁶ and 3D integration of 2D channel FETs⁸⁷ have been recently demonstrated, most of the contact engineering techniques have been developed for planar-structured 2D channel FETs. Several attempts have been made to provide an overview of contact engineering technologies of 2D semiconductors.^88–90 However, their adaptability to GAAFETs still needs to be investigated. In this review, we will look into the contact innovative instances that enabled such progress and provide insights into their applicability for the structure of 3D GAAFETs.

2. Origins of high contact resistance at metal/2D semiconductor junctions

2-1. Interfaces between metals and 2D semiconductors: van der Waals gap and surface contamination

During the fabrication processes where metal–semiconductor junctions are established, the metal–semiconductor interface is susceptible to contamination. This contamination can be induced by adsorption of atmospheric gases^91,92 or polymeric residues^93,94 during fabrication processes (Fig. 2(a)). These contaminants not only prevent direct contact between metals and semiconductors but also lead to inadvertent changes in the electrical properties of semiconductors,^93,95 thereby deviating the metal–semiconductor interfaces from their ideal configurations. Furthermore, reactive metals such as Ti, Cr, and Ir are prone to react with underlying 2D semiconductors and form an intermediate layer between metals and 2D semiconductors (Fig. 2(b)).^96,97 This reaction could be beneficial for achieving lower resistance,⁹⁸ similar to the successfully introduced silicidation process in Si technology.^99,100 On the other hand, it can also degrade the contact interface and overall contact resistance. Thus, the reactivity of contact metals with 2D semiconductors should also be considered to form desirable metal–2D semiconductor contacts. In addition, there exists a physical separation between metals and 2D semiconductors due to the absence of dangling bonds on 2D semiconductors (Fig. 2(c)). This separation is called the van der Waals (vdW) gap and acts as an additional tunnelling barrier, further increasing the contact resistance.^78,101 Utilization of inert metals such as gold (Au) can lead to the formation of type 1 junctions, whereas utilization of more reactive metals can lead to the formation of type 2 and type 3 junctions (Fig. 2(e) and (f)). Type 2 junctions represent metal/2D semiconductor junctions with medium bonding, where vdW gaps are negligible (Fig. 2(e)). Type 3 junctions indicate metal/2D semiconductor junctions with strong bonding, where 2D semiconductors under contact are metallized and vdW gaps vanish (Fig. 2(f)).

Fig. 2 (a) The surface of WSe₂ before and after cleaning the post-lithography polymer residue. Reprinted from ref. 93 with permission from John Wiley and Sons. (b) Reactivity of gold (Au), iridium (Ir), chromium (Cr), and scandium (Sc) with MoS₂. While Au forms van der Waals (vdW)-type contacts with MoS₂, Ir, Cr, and Sc react with MoS₂. Reproduced from ref. 96. (c)–(f) Schematic of metal/2D semiconductor junctions. (d) Type 1 indicates junctions with large vdW gaps and weak interaction, (e) type 2 indicates junctions with medium interaction and (f) type 3 indicates junctions with strong interaction. Reprinted from ref. 101. (g) Fermi-level pinning (FLP) phenomenon due to interface states. Reprinted from ref. 102 with permission from AIP Publishing. (h) Defect-induced gap-states (DIGS) from sulphur (S) vacancies and molybdenum (Mo) vacancies in MoS₂. Reprinted from ref. 103 with permission from IOP Publishing. (i) dI/dV profiles of Au–MoS₂ junctions, indicating gap states decaying with respect to the distance from the contact edge. Reprinted with permission from ref. 104. Copyright 2017 American Chemical Society.

2-2. Fermi-level pinning phenomenon due to MIGS and DIGS

When metals and semiconductors are in contact and in equilibrium, their Fermi level aligns through the transfer of charged carriers from one side to another. However, when there are numerous amounts of interface states within the forbidden gap of semiconductors (gap states) (Fig. 2(g)),¹⁰² a slight change in Fermi-level at the semiconductor surface can generate enough carriers that compensate for the Fermi-level difference. Therefore, the position of the Fermi-level at metal–semiconductor junctions rarely changes, regardless of a metal's Fermi-level. This phenomenon is called Fermi-level pinning (FLP) and it prevails in most metal–semiconductor junctions. The gap states exhibit either donor-like or acceptor-like states based on their charging behavior. When filled with electrons, acceptor-like states are negatively charged, whereas when empty, donor-like states are positively charged. Thus, charge neutrality necessitates the Fermi level of metals at metal/semiconductor junctions to align approximately with the branching point between acceptor-like and donor-like states. This branching point is referred to as the charge neutrality level (CNL), around which the Fermi level of metals at metal/semiconductor junctions is pinned.^105–107 Typically, these gap states are classified as defect-induced gap states (DIGS) and metal-induced gap states (MIGS), according to their origins. Despite the dangling-bond-free nature of 2D semiconductors, native defects such as transition metal vacancies or chalcogen vacancies exist.¹⁰⁸ Furthermore, defects can be generated during fabrication processes such as metal deposition.¹⁴ These defects can induce electronic states within the band gap (DIGS) (Fig. 2(h)).¹⁰³ Similarly, metal contacts can also induce gap states. The wavefunctions of metal electrons can penetrate the semiconductor, decaying exponentially with respect to the distance from the interface (Fig. 2(i)).^104,109 These exponentially decaying wavefunctions can have electronic states within the bandgap of semiconductors that correspond to the virtual gap states of the complex band structure of the semiconductors.¹¹⁰ Briefly, metal electrons’ wavefunctions penetrate the semiconductors, inducing exponentially decaying gap states (MIGS).^104,109,110 DIGS and MIGS are responsible for the FLP phenomenon, forming a non-ideal Schottky barrier height (SBH) and leading to higher contact resistance.

3. Efforts to reduce contact resistance at metal/2D semiconductor junctions

3-1. Contact interface engineering

As aforementioned, the interface contaminants, the vdW gaps, and the FLP phenomenon play a major role in determining contact resistance. Among these, the FLP phenomenon (non-ideal SBH formation) is the main contributor to the high contact resistance issue occurring in metal/2D semiconductor junctions. Unlike Si technology, where the contact resistance can be greatly reduced through doping,¹¹¹ no established doping techniques exist for 2D semiconductors. Therefore, alleviating the FLP phenomenon has been recognized to be crucial for overcoming the high contact resistance issue in 2D semiconductors. Utilization of interlayers at the contact interfaces can separate metals and 2D semiconductors, thereby suppressing the MIGS. Furthermore, it can protect 2D semiconductors during the fabrication process and provide clean contact interfaces, reducing the DIGS.

3-1-1. Metal–insulator–semiconductor contacts. Insulators can serve as effective contact interlayers, physically separating metals and 2D semiconductors. Because insulators have a larger bandgap and lower density of states than semiconductors, they suppress MIGS when used as contact interlayers (Fig. 3(a)).¹⁵

Fig. 3 (a) Schematic of metal–insulator–semiconductor (MIS) contacts. MIGS are suppressed by inserting insulators and the interaction between metals and insulators can change the relative workfunctions of metals to semiconductors. Reprinted with permission from ref. 15. Copyright 2016 American Chemical Society. (b) Surface of 2D semiconductors protected by insulators during the metallization process and a transmission electron microscopy (TEM) image of the Ti/ZnO/MoS₂ interface. Reprinted with permission from ref. 16. Copyright 2020 American Chemical Society. (c) Specific contact resistivity of Ti/Ta₂O₅/MoS₂ junctions versus thickness of Ta₂O₅. Reprinted with permission from ref. 15. Copyright 2016 American Chemical Society. (d) Band diagram of MIS contacts with different conduction band offsets (CBO). ZnO shows a lower CBO than Al₂O₃, leading to lower tunneling resistance. Reprinted with permission from ref. 16. Copyright 2020 American Chemical Society.

Furthermore, insulators can protect underlying 2D semiconductors during the metal deposition process (Fig. 3(b)),¹⁶ reducing the generation of defects and DIGS. Consequently, the FLP phenomenon can be mitigated through the insertion of thin insulating layers. This contact strategy is called metal–insulator–semiconductor (MIS) contacts.^15–18 One of the notable features of MIS contacts is that the interaction between metals and insulators forms interfacial dipoles and alters the relative work functions of metals to semiconductors.^17,18 Cui et al. have reported that the work function of cobalt (Co) film on monolayer h-BN is 3.3 eV, which is 1.7 eV smaller than that of isolated Co.¹⁷ Similarly, Wang et al. have reported that the SBH decreases from 159 to 31 meV when few layer h-BN is inserted between Ni and MoS₂, even though the Schottky–Mott rule^14,112–114 would expect higher SBH for Ni–MoS₂ junctions.^18,89 Certainly, the thickness of insulators is one of the key factors in designing MIS contacts. As the thickness of insulators increases, the FLP phenomenon weakens more due to the greater suppression of MIGS, leading to a lower SBH. However, overall contact resistance may increase with thicker insulators due to increased tunnelling resistance across the insulators. Therefore, MIS contacts have the optimal insulator thickness for minimizing overall contact resistance (Fig. 3(c))^15,16 and lowering tunnelling resistance is crucial for achieving low contact resistance in MIS contacts. Since tunnelling probability is also related to the height of the tunnelling barrier, a band offset between insulators and semiconductors should be considered when designing MIS contacts. Jang et al. have demonstrated that MIS contact with ZnO displays a lower contact resistance than that of Al₂O₃ due to a lower conduction band offset (Fig. 3(d)).¹⁶ Although MIS contacts exhibit small SBH on the order of a few tens of meV, reported instances demonstrate relatively high contact resistance on the order of several kΩ μm. (Table 1). Furthermore, in the advanced technological nodes, integrating insulators thick enough to prevent the FLP phenomenon can be challenging due to the limited space available for forming metal contacts. Thus, low contact resistance with ultrathin insulators should be achieved for the practical utilization of MIS contacts in advanced technological nodes.

Table 1 Comparison table for MIS contacts, vdW contacts, vdW-type contacts, edge contacts, and semimetal contacts

Method	Channel material	Contact material	Type	Contact resistance [kΩ μm]	Schottky barrier height [meV]	On-current [μA μm^−1]	L [μm]	Ref.
IRDS Si HP target (2037)	Si	—	—	<0.105	—	753	0.012	83
IRDS Si HD target (2037)						547
MIS contact	Exfoliated 1L MoS2	h-BN/Co	n	3.8	16	∼1 (VDS = 0.01 V)	0.2	17
	Exfoliated 4–5L MoS2	h-BN/Ni	n	1.8	31	330 (VDS = 5 V)	0.3	18
	Exfoliated 8 nm MoS2	ZnO/Ti	n	0.9	32	<1.5 (VDS = 0.5 V)	2	16
	CVD 4L MoS2	Ta2O5/Ti	n	—	29	—	1	15
VdW contact	Exfoliated 7 nm WSe2	NbWSe2/Ti	p	0.3	—	320 (VDS = −1.5 V)	0.27	19
	Exfoliated 12 nm WSe2	NbMoS2	p	<5	—	4.8 (VDS = −0.1 V)	16	22
	Exfoliated 8–12 nm WSe2	Cl–SnSe2	p	114	780	>4 (VDS = 1 V)	—	23
	CVD 1L MoS2	NbS2/Cr	n	<7500	—	—	10	20
	CVD 1L WSe2	1T′-WS2/Au	p	3.07	50	<1.1 (VDS = 1 V)	15	25
	CVD 1L MoS2	WTe2/Ti	n	67	100	0.244 (VDS = 1 V)	15	27
	CVD 1L WSe2	WTe2/Ti	p	—	71	—	—	21
	CVD 2L WSe2	VSe2/Cr	p	<0.25	—	1580 (VDS = 1 V)	0.02	24
	CVD 5–6 L MoTe2	1T′-MoTe2/Au	p	0.7	14	7.8 (VDS = −1 V)	2	26
	Exfoliated 2L MoS2	ZrTe2/Au	n	—	−13.4	259 (VDS = 2 V)	0.25	28
	Exfoliated 5–6 nm MoS2	Graphene/Ti/Au	n	3.7	—	161 (VDS = 4 V)	1	29
	Exfoliated 16 nm MoS2	Graphene/Ni	n	0.26	300	>4.5 (VDS = 0.2 V)	1	30
	Exfoliated 5L MoS2	Graphene/Cr/Au	n	7.5	—	—	0.035	31
	Exfoliated 1L MoS2	Graphene	n	4.8	—	8.1 (VDS = 0.1 V)	0.008	32
	CVD 1L MoS2	Graphene	n	115	0.19	—	4	33
VdW-type contact	Exfoliated 2L WSe2	Pd/Au	p	3.5	—	>5 (VDS = 0.1 V)	1	34
	Exfoliated <10 nm WSe2	In	n	—	−23	<1 (VDS = 0.1 V)	2.5	36
	Exfoliated <10 nm WSe2	Ti	n	—	64	<0.01 (VDS = 0.1 V)	7.4
	Exfoliated <10 nm WSe2	Au	p	—	120	<1 (VDS = 0.1 V)	2.9
	Exfoliated <10 nm WSe2	Pd	p	—	−15	>1 (VDS = 0.1 V)	2.9
	Exfoliated <10 nm WSe2	Pt	p	—	−45	0.1 (VDS = 0.1 V)	2.6
	CVD 1L WSe2	Au	p	9	47	>3 (VDS = 1 V)	7.8	37
	Exfoliated 1L WSe2	Pt/Au	p	5	—	7.4 (VDS = −1 V)	3	39
	CVD 1L WSe2	Au	—	10.2	—	—	—	41
	CVD 1L WSe2	Pd	—	5.3	36	—	—
	CVD 1L WSe2	Ag	—	2.75 × 10^4	116	—	—
	CVD 1L WSe2	Ti	—	3900	103	—	—
	CVD 1L MoS2	In/Au	n	3.3	—	18 (VDS = 1 V)	2	35
	CVD 1L WSe2	Pt	p	229	400	7.6 (VDS = 1 V)	1.5	40
	Exfoliated 4–20 nm MoS2	Ag	n	—	20	660	0.16	14
VdW-type contact	Exfoliated 4–20 nm MoS2	Pt	p	—	67	210	0.14	14
	Exfoliated 12 nm WSe2	Au	p	1.25	60	—	1.6	38
Edge contact	CVD 2L MoS2	Ni	n	31	—	—	—	42
	Exfoliated 1L MoS2	Ti	n	8.3	—	50 (VDS = 3 V)	1	43
	Exfoliated 4.6 nm MoS2	Mn	n	∼700	—	—	—	46
	Exfoliated 7.5 nm MoS2	Pd	p	—	10	3.9 (VDS = 1 V)	9	44
	Exfoliated 82 nm MoS2	Au	p	—	−16	3.5 (VDS = 1 V)	10
	Exfoliated <10 nm WSe2	In	p	—	74	—	—	45
	Exfoliated <10 nm WSe2	Cr	p	—	70	—	—
	Exfoliated <10 nm WSe2	Pd	p	—	36	—	—
	CVD 1L MoS2	Ni	n	—	850	—	—	47
	CVD 1L MoS2	Ti	n	—	210	—	—
Semimetal contacts	CVD 1L MoS2	Bi	n	0.123	0	1135 (VDS = 1.5 V)	0.035	12
	CVD 1L MoS2	Sb	n	0.042	−10	1440 (VDS = 1 V)	0.02	13
	CVD 1L MoS2	Sb/Au	n	0.300	—	>200 (VDS = 1 V)	0.1	66
	CVD 1L MoS2	Sb/Au	n	0.66	—	600 (VDS = 1 V)	0.05	67
	CVD 1L MoS2	Sn/Au	n	0.84	30	480 (VDS = 1 V)	0.035	68
	CVD 1L MoS2	Bi/Au	n	0.28	0	461 (VDS = 1 V)	0.06	69
	CVD 1L WS2	Bi/Ti/Au	n	1.3	40	245 (VDS = 4.1 V)	0.32	70
	CVD 1L MoS2	Bi	n	0.111	0	1316 (VDS = 2.5 V)	0.2	71

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3-1-2. Van der Waals contacts. Metallic 2D materials can serve as contact interlayers as well, offering advantages over insulators in achieving lower contact resistance due to their intrinsic conductivity.¹¹⁵ Additionally, they interact with 2D semiconductors through the weak vdW forces, providing atomically sharp contact profiles separated by the vdW gaps (Fig. 4(a)). Therefore, the contact strategy utilizing metallic 2D materials refers to vdW contacts and eliminates the FLP phenomenon.^{19–27,116,117} VdW contacts between diverse 2D semiconductors and various metallic 2D materials, including heavily doped 2D semiconductors,^19,22,23 inherently (semi)metallic 1T(′)-phase TMDs,^{20,21,24–28,116,117} and graphene^29–33 have been investigated. The reported instances have demonstrated a wide range of contact resistance (Table 1), a consequence of the broad range of work functions offered by 2D materials (Fig. 4(b))^118–120 and the absence of the FLP phenomenon in vdW contacts (Fig. 4(c)).²⁷ Hence, it is crucial to carefully choose appropriate metallic 2D materials tailored to a specific 2D semiconductor to ensure low SBH and contact resistance. Utilizing graphene contacts is also advantageous in this regard. This is because the SBH between 2D semiconductors and graphene is modulated by electrostatic doping^29,31 or charge transfer from metals.^30,33 The Fermi-level of graphene is shifted largely by doping due to the negligible DOS around its Dirac point. VdW contacts can be achieved by transferring 2D materials onto each other (Fig. 4(d)).^{19,20,22,23,25,27,29–33,116} While this fabrication method is useful for quickly testing various vdW contacts and can circumvent thermal budgets through recent advancements in the transfer process of various 2D materials,^121,122 it may induce larger vdW gaps, degrading overall contact resistance. Shim et al. have reported WTe₂-contacted WSe₂-channel transistors and compared them with palladium (Pd)-contacted WSe₂-channel transistors.¹¹⁶ Devices with WTe₂ contacts exhibit significantly lower electron and hole currents than Pd-contacted devices. This presents a substantial series resistance in WTe₂-contacted devices, rather than the existence of a higher SBH at WTe₂–WSe₂ junctions compared to Pd–WSe₂ junctions. Furthermore, transferring 2D materials would not be applicable for advanced transistor structures such as GAAs. In contrast to the transfer, direct growth of metallic 2D materials is desirable, providing clean contact interfaces with minimal vdW gaps (Fig. 3(e)).^21,24,117 Notably, Wu et al. have demonstrated that metallic VSe₂ can be grown directly on bilayer-WSe₂, achieving a low contact resistance less than 0.25 kΩ μm and a high on-current exceeding 1.5 mA μm⁻¹ (Fig. 4(e) and (f)).²⁴ This on-current is among the highest values achieved thus far, even comparable to that of the Si transistors.⁸³ However, growth of metallic 2D materials on 2D semiconductors at precise positions in the wafer-scale would be challenging, considering the current immature state of the wafer-scale growth technology for 2D materials.¹²³ Nevertheless, their result suggests that vdW contacts, with the appropriate process technology suitable for mass production, have potential in enabling low contact resistance for 2D semiconductors.

Fig. 4 (a) Cross-sectional TEM images of Pd–WSe₂ junctions and Cl–SnSe₂/WSe₂ junctions. Cl–SnSe₂/WSe₂ junctions show intact interfaces while Pd–WSe₂ junctions show damaged interfaces during the metallization process. Reprinted from ref. 23 with permission from John Wiley and Sons. (b) Workfunctions of various metallic TMDs with respect to the conduction band minimum (CBM) and valence band maximum (VBM) of MoS₂ and WS₂. Reprinted from ref. 120 with permission from John Wiley and Sons. (c) Schottky barrier height (SBH) between MoS₂ and various metallic 2D materials, indicating suppressed Fermi-level pinning (FLP) phenomenon in vdW contacts. Reprinted from ref. 27 with permission from Springer Nature. (d) 1T′-MoTe₂/2H-MoTe₂ vdW contacts enabled by transferring 1T′-MoTe₂ onto 2H-MoTe₂ with atomically clean interfaces. Reprinted from ref. 26 (e) VSe₂–WSe₂ vdW contacts and (f) transfer curve of VSe₂ contacted WSe₂ channel FETs, displaying a high on-current exceeding 1.5 mA μm⁻¹. Reprinted from ref. 24 with permission from Springer Nature. (g) Schematic illustration of vdW-type contacts enabled by the transfer process and metal/2D semiconductor junctions formed by the conventional evaporation process. Reprinted from ref. 14 with permission from Springer Nature. (h) Electron barrier versus metal workfunctions of vdW-type contacts and evaporated contacts. VdW-type contacts show suppressed FLP phenomenon. Reprinted from ref. 14 with permission from Springer Nature. (i) Scanning transmission electron microscopy (STEM) image of vdW-type Au–WSe₂ junctions and directly deposited Au–Wse₂ junctions. VdW-type Au–WSe₂ junctions display enlarged vdW gaps. Reprinted from ref. 38 with permission from Springer Nature.

3-1-3. Van der Waals-type contacts. Conventional metals also establish junctions with 2D semiconductors, separated by the vdW gaps. These junctions can be achieved through a non-destructive formation of metals with minimal interaction with 2D semiconductors (Fig. 4(g)). This type of contacts is referred to as vdW-type contacts, and it can successfully eliminate the FLP phenomenon (Fig. 4(h)).^{14,34–41,124} VdW-type contacts can be achieved through various methods including transfer^{14,34,36,37,39,124} and utilization of decomposable buffer layers.^38,41 However, these methods would not be suitable for advanced transistor structures such as GAA, where contacts need to be formed in limited and intricate 3D spaces, as discussed earlier. Therefore, vdW-type contacts with a direct metal deposition method would be more desirable. As vdW-type contacts can be established by minimizing the defect generation during the metallization process, selecting metals with low sublimation energy³⁵ or optimizing the metallization process⁴⁰ can lead to the formation of vdW-type contacts without relying on a transfer process or additional layers. Wang et al. reported that metals with low sublimation energy, such as indium (In), can form vdW-type contacts with 2D semiconductors through direct deposition.³⁵ Notably, they also discovered that even high workfunction metals, such as platinum (Pt), can be gently deposited on 2D semiconductors without causing damage to them, when the sample temperature is maintained at room temperature.⁴⁰ Their discovery indicates that any metal/2D semiconductor junctions could follow the Schottky-Mott rule if process conditions are optimized. The reported vdW-type contacts showed a relatively high contact resistance ranging from several kΩ μm to tens of kΩ μm (Table 1). This may be attributed to enlarged vdW gaps in vdW-type contacts, as Kwon et al. reported that vdW-type gold (Au)–WSe₂ junctions exhibit larger vdW gaps than directly deposited Au–WSe₂ junctions (Fig. 4(i)).³⁸ These findings from vdW-type contacts highlight that achieving clean contact interfaces with minimal vdW gaps is crucial to accomplish ultra-low contact resistance for 2D semiconductors.

3-2. Edge contacts

Due to the large area-to-volume ratio of 2D semiconductors, metal/2D semiconductor junctions are typically formed on the surface of 2D semiconductors. However, surface contacts can often result in severe FLP phenomenon or the presence of large vdW gaps, leading to high contact resistance, as discussed earlier. Since 2D semiconductors consist of covalent bonds in the in-plane directions, there are unterminated bonds at their edges, similar to conventional semiconductors. When metals contact the edges, covalent bonds form between the metals and 2D semiconductors, eliminating vdW gaps (Fig. 5(a)).¹⁰¹ This contact strategy is called edge contacts and facilitates carrier injections from metals to semiconductors and vice versa, through strong interaction between metals and 2D semiconductors.^42–45,101 Furthermore, theoretical studies have revealed that reduced contact dimensionality leads to alleviated FLP phenomenon. When gap states, which are responsible for FLP phenomenon, are charged by carriers, they can induce image charges on metal sides and form an interface dipole. In edge contacts, these dipoles are spatially localized in 1D contact interfaces and form a line of dipoles, inducing an electric field much weaker than that of a sheet of dipoles^{46,47,125–127} (Fig. 5(b)). Thus, the FLP phenomenon can be effectively alleviated in edge contacts. Alleviated FLP phenomenon was confirmed in various experimental studies.^42,43,46,47 Yang et al. have demonstrated the suppressed FLP phenomenon in edge contacted metal/multilayer-MoS₂ junctions (Fig. 5(c)).⁴⁴ Hung et al. have reported that edge contacts can effectively suppress FLP phenomenon even for monolayer MoS₂.²¹ Consequently, the quality of the contact interface remains crucial to suppress the FLP phenomenon in edge contacts. During the fabrication process, the edges of 2D semiconductors can be exposed to contaminants, which leads to stronger FLP phenomenon. Ngo et al. reported that non-stoichiometric WO_x can form at the edges of WSe₂ and it induces stronger FLP as WO_x has a high workfunction (Fig. 5(d)).⁴⁵ Notably, edge contacts are immune to contact length scaling, as their contact area does not change with contact length. Cheng et al. demonstrated that the on-current of edge-contacted MoS₂ devices does not decrease even though the contact length shrinks to 20 nm (Fig. 5(e)).⁴² However, edge contacts typically show higher contact resistance than surface contacts (Table 1), as edge contacts cannot provide sufficient contact area.⁴⁶ Surface contacts alone would not provide sufficiently low contact resistance, either, due to the limited contact space in advanced technological nodes. Therefore, wrap-around contacts that integrate edge and surface contacts might be more desirable to maximize the contact area and ensure low contact resistance, as Chung et al. have recently demonstrated in MoS₂-channel devices.¹²⁸

Fig. 5 (a) Schematic diagram of edge contacts and high-resolution transmission electron microscopy (HR-TEM) image of edge contacted MoS₂. Reprinted from ref. 44 with permission from John Wiley and Sons. (b) Relative energy level of the conduction band minimum with respect to the Fermi level of ideal, top contacted, and edge contacted junctions. Reprinted from ref. 47 with permission from IEEE. (c) The workfunction of metals and band alignment of top contacted and edge contacted metal/2D semiconductor junctions, indicating reduced FLP phenomenon in edge contacts. Reprinted from ref. 44 with permission from John Wiley and Sons. (d) Cross sectional HRTEM image of edge contacted metal–WSe₂ junctions, displaying the presence of WO_x at the interface, transfer characteristics of edge contacted WSe₂-channel devices and surface contacted WSe₂-channel devices, indicating persistent p-type characteristics in edge contacted devices, and hole SBH versus metal workfunctions. Reprinted from ref. 45 with permission from Royal Society of Chemistry. (e) Contact length scaling for nickel (Ni) edge contacted MoS₂-channel devices, showing immunity to contact length scaling down to 20 nm. Reprinted with permission from ref. 42. Copyright 2019 American Chemical Society.

3-3. Doping

Heavily doped semiconductors can readily form Ohmic junctions with various metals, as carriers can easily tunnel thin barriers (Fig. 6(a)). In Si technology, this can be achieved by substituting Si atoms with group III or group V elements.¹²⁹ However, an ion implantation, which is mostly used to dope the Si, is not readily applicable for atomically thin 2D semiconductors due to substantial defect generation during an ion bombardment process (Fig. 6(b)),¹³⁰ prompting the exploration of alternative doping approaches. Since the early stage of doping research for 2D semiconductors, chemical doping has been explored due to their facileness (Table 2).^48–56 Although utilization of chemicals has proven useful in inducing heavy doping on 2D semiconductors and achieving low contact resistance (Fig. 6(c) and (d)), they often suffer from poor stability and controllability, making them unsuitable for practical applications. More stable doping of 2D semiconductors can be achieved using solid-state oxide layers. Solid-state oxides can induce substantial charges on 2D semiconductors, providing more stable heavily doped 2D semiconductors (Table 2).^{57–64,131,132} Notably, WO_x can be formed by oxidizing tungsten (W)-based TMDs, inducing substantial hole doping on the remaining W-based TMDs. Furthermore, WO_x can be formed through a self-limiting oxidation process, making a sophisticated layer-by-layer oxidation of W-based TMDs possible (Fig. 6(e)).^58,60,62,132 Huang et al. have demonstrated that this layer-by-layer oxidation of bilayer WSe₂ can be utilized to establish a WO_x spacer, inducing heavy hole doping on the spacer region of WSe₂-channel FETs (Fig. 6(f)).⁶² However, doping the contact area through solid-state oxides is challenging, as inserting them between metals and 2D semiconductors leads to undesirable resistance.⁵⁹ In contrast to this, substitutional doping can induce substantial charges on 2D semiconductors without an additional layer. In situ substitutional doping, where dopant atoms are incorporated into lattice structures during their growth, is available for 2D semiconductors. This technique provides the most stable heavily doped 2D semiconductors, compared to the other approaches (Table 2).^65,133–136 However, with this in situ substitutional doping technique, selectively doping a specific area of 2D semiconductors is challenging. Therefore, a regrowth strategy, where heavily doped 2D semiconductors for contacts and intrinsic 2D semiconductors for channels are grown separately, could be useful to circumvent this challenge, as Gao et al. have demonstrated (Fig. 6(g)).¹³⁵

Table 2 Comparison table for doping

Method	Channel material	Contact material	Type	Contact resistance [kΩ μm]	Carrier concentration [10^12 cm^−2]	On-current [μA μm^−1]	L [μm]	Ref.
IRDS Si HP target (2037)	Si	—	—	<0.105	—	753	0.012	83
IRDS Si HD target (2037)						547
NO2 doping	Exfoliated 1L WSe2	Pd	p	—	2.2	<10 (VDS = −1 V)	9.4	48
BV doping	Exfoliated 5 nm MoS2	Ni/Au	n	1.1	12	8 (VDS = 0.05 V)	0.42	49
Cl doping	Exfoliated 5–7L WS2	Ni	n	0.7	0.6	380 (VDS = 2 V)	0.1	50
Cl doping	Exfoliated 5–7L MoS2	Ni	n	0.5	9.2	460 (VDS = 2 V)	0.1
NO2 doping	Exfoliated 7 nm WSe2	Pd	p	1.27	11.2	—	0.5	51
LiF doping	Exfoliated 5.3 nm WS2	Cr/Au	n	0.93	—	65 (VDS = 1 V)	0.5	52
AuCl doping	Exfoliated 7–11 nm MoS2	Pd/Au	p	2.3	1.5	21	1	53
Nbm doping	Exfoliated 1L MoS2	Au	n	4.4	2.18	83.4 (VDS = 1 V)	0.5	54
Carbonyl compound doping	CVD 1L MoS2	Au	n	1.2	41	—	—	55
HAuCl4 doping	CVD 1L WSe2	Pd	p	0.7	17.6	~10 (VDS = −1 V)	5	56
ATO doping	Exfoliated 1L MoS2	Ag/Au	n	0.18	7.4	240 (VDS = 2 V)	0.45	57
AlOx doping	CVD 1L MoS2	Au	n	0.48	20	300 (VDS = 1 V)	0.38	61
SiOx doping	CVD 1L MoS2	Pd	n	4.5	14	—	5	63
WOx doping	CVD 1L WSe2	Pd/Au	p	1.45	0.6	1 (VDS = 0.1 V)	0.5	64
WOx doping	Exfoliated 4L WSe2	Ti/Au	p	1.4	2.6	—	—	58
WOx doping	Exfoliated 8L WSe2	Ti/Pd	p	0.528	8.3	320 (VDS = −1 V)	0.07	60
WOx doping	CVD 2L WSe2	Pd	p	1	—	>10	0.5	62
MoOx doping	Exfoliated few L WSe2	Pt	p	0.8	20	1000 (VDS = 5 V)	0.4	59
Fe doping	CVD 1L MoS2	Cr/Au	n	0.678	76	—	10	65

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Fig. 6 (a) Band diagram of undoped (black) and doped (red) metal–semiconductor junctions. The tunnelling current increases in doped junctions through a thinned barrier due to doping. (b) A schematic of an ion implantation system and thickness reduction of MoS₂ flakes measured by atomic force microscopy, due to an ion implantation process. Reprinted with permission from ref. 130. Copyright 2016 American Chemical Society. (c) A schematic diagram of NO₂ doped WSe₂ channel FETs and their transfer characteristics, indicating heavily doped WSe₂. Reprinted with permission from ref. 48. Copyright 2012 American Chemical Society. (d) Schematic diagram of Cl doped TMDs and contact resistance of doped Ni–WS₂ and Ni–MoS₂ junctions. Reprinted with permission from ref. 50. Copyright 2014 American Chemical Society. (e) Self-limiting oxidation of WSe₂ by O₃ treatment. Reprinted with permission from ref. 132 (f) P-MOSFET enabled by self-limiting oxidation of bilayer WSe₂. Only the top layer was oxidized and induce hole doping on underlying WSe₂. Reprinted with permission from ref. 62. (g) Nb-doped MoS₂ and pristine Mos₂ junctions formed by regrowing intrinsic MoS₂ after etching Nb-doped MoS₂. Reprinted with permission from ref. 135. Copyright 2020 American Chemical Society.

3-4. Semimetal contacts

MIGS, one of the main contributors of the FLP phenomenon, are induced by the penetration of electron wavefunctions from metals into semiconductors when metal/semiconductor junctions are formed.^109,110 In contrast to metals, which possess a significant density of states (DOS) around their Fermi level, semimetals have a negligible DOS at their Fermi level, resulting in significantly reduced MIGS. According to the theory of MIGS, MIGS are contributed by either the conduction band or valence band. Conduction band-contributed MIGS are acceptor-like states and the valence band-contributed MIGS are donor-like states.¹⁰⁷ When semimetals come into contact with semiconductors and the Fermi level of semimetals is close to the conduction band minimum of semiconductors, the contribution of the conduction band to MIGS is greatly reduced and MIGS are mainly contributed by the valence band. This shifts the branching point of MIGS, where the Fermi-level of metals is pinned around,¹⁰⁷ into the conduction band (Fig. 7(a)).¹² Therefore, the SBH of the junctions vanishes and semiconductors under contact become heavily doped by electrons, leading to ohmic contacts.^{12,13,66–70,137–140} Furthermore, as semimetals typically have a low melting point, vdW-type contacts are achievable with semimetals, leading to clean contact interfaces (Fig. 7(c)).⁶⁶ Shen et al. have reported that semimetal bismuth (Bi) (0001) can form ohmic junctions with MoS₂, reporting a negligible SBH, low contact resistance of 123 Ω μm, and high on-current of 1135 μA μm⁻¹,¹² even comparable that of the state-of-the-art Si transistors.⁸³ They have also noted that the quality of channel material is crucial to achieve low contact resistance with semimetal contacts, since DIGS from high defect density can affect the Fermi level pinning. The crystal orientation of semimetals also affects the contact resistance. Li et al. demonstrated that semimetal antimony (Sb) (011̄2)–MoS₂ junctions can outperform Sb (0001)–MoS₂ junctions, as Sb (011̄2) has a higher atomic density than Sb (0001), leading to stronger interaction between Sb (011̄2) and MoS₂ (Fig. 7(b)).¹³ This results in an ultra-low contact resistance of 42 Ω μm and high on current of 1.23 mA μm⁻¹, which even outperforms that of the state-of-the-art Si technology.⁸³ Notably, semimetal contacts also exhibit a short transfer length.^12,13 Wu et al. demonstrated that the contact length of Sb–MoS₂ junctions can be scaled down to 12 nm without degrading performance when process conditions are optimized to ensure a minimal vdW gap (Fig. 7(d)).⁶⁶ Thus far, semimetal contacts have only been demonstrated for achieving n-type ohmic contacts, as elemental semimetals typically have a low workfunction. p-Type ohmic contacts can be achieved, if semimetals’ workfunction aligns with the valence band maximum of 2D semiconductors, as Yang et al. have theoretically demonstrated.¹⁴¹ They have also noted that high workfunction semimetals such as Co₃Sn₂S₂ and TaP can form ohmic contacts for holes with WSe₂. Even though semimetal contacts offer ultralow contact resistance, they encounter challenges regarding their poor thermal stability due to their low melting point, especially for Bi (271.5 °C). Although Sb shows better thermal stability due to its higher melting point (630.6 °C), the performance of Sb–MoS₂ junctions starts degrading at 300 °C (Fig. 7(e)).⁶⁷

Fig. 7 (a) Schematic diagram of metal/semiconductor junctions and semimetal/semiconductor junctions. Junctions with semimetals show suppressed MIGS and almost zero SBH. Reprinted from ref. 12 with permission from Springer Nature. (b) Electrical properties of antimony (Sb) (011̄2)–MoS₂ junctions and Sb (0001)–MoS₂ junctions, indicating the superior performance of Sb (011̄2)–MoS₂ junctions. Reprinted from ref. 13 with permission from Springer Nature. (c) vdW-type contacts between Sb and MoS₂ due to the low melting point of Sb. Reprinted from ref. 66 with permission from IEEE. (d) Contact length scaling of Ni- and Sb–MoS₂ junctions, indicating superior immunity to the contact length scaling of Sb–MoS₂ junctions. Reprinted from ref. 66 with permission from IEEE. (e) Contact resistance of bismuth (Bi)– and Sb–MoS₂ junctions versus annealing temperature. The performance of Sb–MoS₂ junctions starts degrading at 300 °C. Reprinted from ref. 67 with permission from IEEE.

4. Perspectives and conclusions

We have discussed the potential of 2D semiconductors as an alternative channel material for advanced 3D-structured transistors, such as GAAFETs and CFETs. This potential arises from their decent carrier mobility even at sub 1 nm thickness and much shorter scaling length than that of silicon. However, 2D semiconductors suffer from high contact resistance due to the FLP phenomenon and vdW gaps, significantly degrading their on-current and circuit level performance. Moreover, addressing this becomes even more formidable in advanced technological nodes, where contacts must be established in intricate and limited 3D spaces. This limitation can restrict options for contact engineering strategies. In this regard, we have reviewed and evaluated the contact engineering technologies for 2D semiconductors such as MIS contacts, vdW and vdW-type contacts, doping-assisted, and semimetal contacts.

Most contact innovations have thus far been accomplished in planar-structured devices with large dimensions. This significantly deviates from advanced 3D transistor structures such as GAAFETs, where contacts need to be formed under limited and complex 3D spaces. This discrepancy could raise questions about their suitability for practical applications. Due to complex 3D space allowed for contacts, the insertion of contact interlayers except metals would not be desirable. Similarly, vdW and vdW-type contacts utilizing a transfer process would also be inapplicable. Furthermore, the shrunken device size in advanced technological nodes leaves not much area reserved for contacts. As most of the contact engineering techniques were reported with very large dimensions, significantly higher contact resistances are predicted when applied to the scaled devices. Therefore, rather than relying solely on surface contact not to provide sufficient contact area, edge or wrap-around contacts based on ALD of various metals need to be explored.

Thus far, significant advancements have been made in lowering contact resistance. In particular, ultra-low contact resistance for electrons has been achieved through the introduction of semimetal contacts, although their thermal stability issues remain. However, the contact resistance for holes remains relatively high, which needs to be improved for practical applications of 2D semiconductors. The findings from various technical innovations concluded that suppression of the FLP phenomenon alone would be insufficient to achieve ultra-low contact resistance. Thus, alternative approaches such as substitutional doping should be considered to achieve ultra-low contact resistance for holes. Finally, it should be emphasized that considering the 3D device structures is very important to achieve reliable results and facilitate the practical integration of 2D semiconductors.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This research was supported by the National Research Foundation of Korea (NRF) (2022M3F3A2A01072215, 2021R1A2C2010026). This work was also supported by the Technology Innovation Program (RS-2023-00235609, Proposal of 3D DRAM development direction from the process development of vertical stacked cell transistors) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) (1415187471). It was also supported by Samsung Electronics Co., Ltd (IO231207-08190-01).

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Footnote

† These authors contributed equally to this work.

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