Stabilization of top-gate p-SnO transistors via ultrathin Al₂O₃ interlayers for hysteresis-free operation

Abstract

The integration of p-type oxide semiconductors is imperative for realization of complementary metal–oxide–semiconductor logic in monolithic 3D integrated circuits. Among the various p-type oxides, SnO has emerged as a promising channel material owing to its high hole mobility and back end of line compatibility. However, its metastable nature and susceptibility to oxidation pose substantial challenges, particularly in top-gate thin-film transistors (TFTs), where the SnO channel is directly exposed to oxidizing species during high-k HfO₂ dielectric deposition. In this study, we introduce an ultrathin Al₂O₃ interlayer (IL) (1.5–3 nm) between the SnO channel and high-k HfO₂ dielectric to mitigate this challenge. The IL enables the use of ozone as an oxidant during HfO₂ deposition while preventing excessive SnO oxidation, and thereby preserving high-performance p-type conduction. Through the optimization of the interlayer thickness, we eliminated the hysteresis behavior and achieved a substantial enhancement in field-effect mobility and improvement in on/off current ratio. This study presents the first demonstration of a top-gate TFT featuring a p-type oxide channel fabricated via atomic layer deposition, enabled by the incorporation of an ultrathin Al₂O₃ interlayer. The findings underscore the pivotal role of interface engineering in the stabilization of p-type oxide semiconductors and provide insights into their practical implementation in advanced electronic devices.

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Introduction

Research on “Beyond Moore” to overcome the downscaling limitations of conventional silicon-based lateral structures has been ongoing. The use of monolithic 3D (M3D) integrated circuits (ICs) is emerging as a promising approach beyond the scaling constraints of 2D structures, providing key advantages such as a higher integration density, lower power consumption, and reduced interconnect delay owing to smaller interconnect lengths.^1–4 Despite these advantages, M3D ICs have not yet been commercialized owing to the limited availability of high-performance channel materials that can meet the stringent low thermal budget (≤400 °C), which is critical to prevent degradation of bottom-tier devices. To explore potential solutions, oxide semiconductors have emerged as promising candidates for M3D IC integration, providing high mobility, low-temperature processability, and compatibility with complementary metal–oxide–semiconductor (CMOS) integration.^1,4,5 However, despite the considerable advances in n-type oxide transistors, progress in p-type oxide transistors remains relatively limited.^4–8

The advancement of transistors based on p-type oxide semiconductors has been hindered by two factors. First, availability of p-type oxide materials capable of achieving high mobility and on/off ratio is limited. Second, optimized device fabrication processes that can fully utilize the potential of p-type oxide semiconductors are lacking. In other words, beyond the development of suitable p-type oxide materials, the advancement of fabrication processes tailored to these materials is equally crucial for the realization of high-performance transistors. This necessity arises as the p-type phase exhibits relative instability compared to the n-type phase, rendering it more vulnerable to alterations in electrical properties during the process of device fabrication.^4,6,9–11 Studies on device fabrication processes designed for the commercialization of p-type oxide semiconductors that adequately consider their metastable characteristics have been limited.

SnO has garnered interest as a promising candidate for next-generation p-type oxide semiconductor applications owing to its high hole mobility, which is attributed to the presence of a valence band maximum owing to the hybridization of the isotropic Sn 5s and oxygen 2p orbitals.^12–14 Various strategies have been explored to enhance the performances of oxide materials, including cation doping,^15,16 microstructure modulation,^17–19 phase engineering,^20,21 and use of oxidation state-controlled atomic layer deposition (ALD) precursors.^14,22,23 There is a clear predominance of research efforts aimed at developing materials, rather than optimizing the overall device fabrication process, as aforementioned. However, as for other p-type oxide semiconductors, SnO cannot entirely avoid phase stability issues, making it particularly susceptible to the postdeposition process. In particular, the Sn⁴⁺ oxidation state in n-type SnO₂ is more stable than the Sn²⁺ oxidation state in SnO, which renders SnO highly susceptible to be oxidized during the integration process.^11,14,24 This instability poses a substantial challenge to the realization of high-performance p-type transistors. Therefore, the development of p-type SnO transistors must extend beyond material optimization to device-level engineering, ensuring both stability and high performance in practical applications.

Targeting M3D IC applications, we aimed to develop a top-gate p-SnO thin-film transistor (TFT) fabrication process utilizing ALD, which provides superior large-area uniformity and precise thickness controllability compared to other deposition techniques.^4,25,26 In addition, the utilization of a high-k material as a gate dielectric was strategically considered, with a focus on facilitating commercialization. Unlike bottom-gate TFT configurations, where the channel is deposited directly onto the gate dielectric, top-gate structures enable a higher flexibility in the choice of the underlying substrate. This flexibility facilitates the optimization of channel properties by allowing the use of tailored buffer layers^17,27 or optimized surface treatments¹⁹ while maintaining compatibility with M3D integration. Moreover, issues such as the hysteresis behavior caused by unintended reactions between the SnO channel and substrate during the deposition process can be mitigated.²⁸ However, despite these advantages, the use of a top-gate structure is hindered by challenges. In industrial applications, high-k HfO₂ dielectrics are commonly deposited via ALD using ozone (O₃) as an oxidant.^29,30 This dielectric deposition process degrades the predeposited SnO channel layer.

In this study, we propose a simple yet effective strategy to prevent surface oxidation and maximize the performance of p-SnO in top-gate TFTs. A thin Al₂O₃ interlayer (IL) was introduced between the high-k HfO₂ dielectric and SnO channel, enabling the use of highly oxidative O₃ as an oxidant for HfO₂ deposition and protecting the SnO surface from oxidation-induced degradation. This approach effectively preserved the integrity of both the HfO₂ dielectric and SnO channel, and thereby provided excellent p-type characteristics of the top-gate TFTs. By optimizing the interlayer thickness, we even successfully eliminated the hysteresis behavior. Furthermore, this approach led to substantial reductions in interfacial organic contamination and gate leakage current, thereby enhancing the overall performance of the device.

Experimental methods

Film growth and device fabrication

SnO thin films were deposited using ALD with Sn(dmamp)₂ and H₂O as a Sn source and oxidant, respectively, at a process temperature of 210 °C and a working pressure of 600 mTorr. The ALD cycle for SnO deposition consisted of a 4-s injection of Sn(dmamp)₂, followed by a 8-s purge, 2-s injection of H₂O, and 10-s purge. Nitrogen gas served as both a carrier for Sn(dmamp)₂ and a purging gas. A 13 nm thick SnO film was employed as a channel layer in the coplanar structured top-gate TFTs. For the source and drain electrodes, nickel/gold (20 nm/30 nm) were deposited via thermal evaporation and e-beam evaporation, respectively. The source/drain electrodes were patterned using the lift-off method. Subsequently, Al₂O₃ interlayers with varying thicknesses were deposited onto the fabricated devices via ALD, utilizing trimethyl aluminum (TMA) and H₂O as an aluminum source and an oxidant, respectively, at 150 °C under a working pressure of 600 mTorr. The ALD cycle for Al₂O₃ consisted of a 1-second injection of TMA, followed by a 10-second purge, a 1-second injection of H₂O, and a 10-second purge. Nitrogen gas served as a purging gas with a flow rate of 200 sccm. The reference device was fabricated without the incorporation of an Al₂O₃ interlayer. For the dielectric layer, HfO₂ was deposited using ALD with tetrakis(ethylmethylamino) hafnium (TEMAHf) as a Hf source and O₃ as an oxidant at a temperature of 260 °C under a working pressure of 800 mTorr. The ALD cycle for HfO₂ consisted of a 3-second injection of the TEMAHf pulse, followed by a 15-second purge, a 5-second injection of O₃, and a 10-second purge. Nitrogen gas also served as a purging gas with a flow rate of 350 sccm. The molybdenum top-gate electrode was fabricated through sputtering at room temperature and patterned using the lift-off method.

Thin-film characterization

The thicknesses of the thin films were measured using spectroscopic ellipsometry (SE, MG-1000, Nano-View) at the 3D Convergence Center of Inha University. The chemical states of the thin films were analyzed using angle-resolved X-ray photoelectron spectroscopy (ARXPS, Nexsa-G2, Thermo Fisher Scientific). The crystal structures of the thin films were examined using X-ray diffraction (XRD, X'Pert-PRO MRD, Philips) and transmission electron microscopy (TEM, JEM-2100F, JEOL). Cross-sectional specimens for TEM analysis were prepared using the focused ion beam technique. Diffraction peak indexing was performed using JCPDS cards 43-1017 for monoclinic HfO₂, 85-0712 for tetragonal SnO, and 41-1445 for tetragonal SnO₂. Impurity profiles of the multilayer films were analyzed by time-of-flight secondary-ion mass spectrometry (TOF-SIMS, TOF.SIMS-5, ION-TOF). For the analysis, a Bi¹⁺ gun with an energy of 30 keV and a current of 1 pA was used, with region of interest dimensions of 40 μm × 50 μm. For sputtering, we employed a Cs+ gun at 1 keV and 10 nA, with raster dimensions of 150 μm × 150 μm.

Device measurements

Characterization of the fabricated top-gate TFTs was conducted at room temperature in a dark box, which blocked electromagnetic wave interference. The semiconducting behaviors of the TFTs were measured using a semiconductor parameter analyzer (2636A, Keithley). The width and length of the SnO channel were 300 μm and 50 μm, respectively. The capacitance of dielectric layers was estimated using an impedance analyzer (MFIA 500 K, Zurich Instruments). The device parameters were measured at V_DS = −0.1 V. The subthreshold swing (SS) was calculated as the average of the seven smallest SS values in the subthreshold region. The field-effect mobility (μ_FE) was calculated using the transconductance and measured capacitance density of the dielectrics. The threshold voltage (V_th) was extracted by plotting the drain current (I_DS) on the y-axis versus the gate voltage (V_GS) on the x-axis, and extrapolating the linear portion of the curve to the x-axis (V_GS).

Results and discussion

Even though ALD SnO exhibits the best p-type switching performance among oxide semiconductors synthesized via various methods,^{4,17,19,22,23,27} its phase instability remains a key challenge to be addressed for industrial applications.^11,14,24Fig. 1(a) illustrates the disproportionation of the SnO thin films under 300 °C annealing in an Ar atmosphere, which can be described by the following reaction:

2SnO → SnO₂ + Sn.

Without the addition of the oxidant, the SnO matrix could even break down into Sn and SnO₂. The increased presence of Sn⁴⁺ from SnO₂ and Sn⁰ from the metallic Sn phase, along with a decrease in Sn²⁺ from SnO, indicates the disproportionation and phase instability of SnO thin films. As evident here, the Sn²⁺ oxidation state is unstable. Upon exposure to oxidants, SnO is readily oxidized to SnO₂, which exhibits the Sn⁴⁺ oxidation state.^11,31 This metastable nature of SnO hinders its application in electronic devices and integration with n-type oxide semiconductors in system designs.

Fig. 1 (a) XPS Sn 3d spectra of the as-grown SnO film and postannealed SnO films at 250 °C and 300 °C under an Ar atmosphere. Reproduced from ref. 14 with permission from the Royal Society of Chemistry. ARXPS Sn 3d spectra of the (b) HfO₂/SnO stack and (c) HfO₂/Al₂O₃/SnO stack. Deconvoluted XPS Sn 3d spectra of the (d) HfO₂/SnO stack and (e) HfO₂/Al₂O₃/SnO stack, measured at θ = 60°.

HfO₂, one of the most widely used high-k dielectrics in the industry, is typically synthesized via ALD using O₃ as an oxidant. In the design of a top-gate SnO TFT with a HfO₂ dielectric, the dielectric film must be deposited directly onto the semiconductor layer, which inevitably exposes the SnO surface to O₃. This exposure is expected to induce surface oxidation. To investigate the extent of SnO surface oxidation via dielectric deposition, we deposited a 3 nm HfO₂ film on the SnO surface and performed an ARXPS analysis. The analysis was conducted at incident angles of 10°–60° to focus on the vicinity of the channel/dielectric interface in SnO. All binding energies for XPS were calibrated to the C–C bond at 284.8 eV. The Sn 3d_5/2 spectra were evaluated at binding energies of 485.9 eV for Sn²⁺ and 486.6 eV for Sn⁴⁺.^14,19Fig. 1(b) indicates that Sn⁴⁺ is observed as prominently as Sn²⁺. At a theta angle of 10°, the intensity ratio at 486.6 eV (Sn⁴⁺) to 485.9 eV (Sn²⁺) is 0.92. However, under more surface-sensitive conditions at a theta angle of 60°, the ratio is increased to 0.97, indicating a higher degree of surface oxidation.

We then considered the insertion of an Al₂O₃ layer to protect the SnO surface during HfO₂ deposition. As H₂O, the same mild oxidant used for SnO deposition, was used for Al₂O₃ deposition, the inevitable surface oxidation was expected to be prevented. In addition, Al₂O₃ has previously been validated as an effective passivation layer in bottom-gate staggered SnO TFTs, where it reduces surface gap states on SnO.^14,32 As expected, when a 1.5 nm Al₂O₃ interlayer was inserted between the 3 nm HfO₂ and SnO films, the intensity of Sn²⁺ was significantly higher than that of Sn⁴⁺, as shown in Fig. 1(c). This indicates that the ultrathin 1.5 nm Al₂O₃ interlayer is effective in preventing the oxidation of the SnO surface. For a more detailed analysis, peak deconvolution was performed using the measured spectrum at 60°, which provides the most surface-sensitive binding energy (Fig. 1(d) and (e)). In the structure where HfO₂ was deposited without an Al₂O₃ interlayer, Sn²⁺/[Sn²⁺ + Sn⁴⁺] was 0.61. In contrast, when an Al₂O₃ interlayer was inserted, this ratio increased to 0.76, indicating that the formation of the Sn⁴⁺ phase was effectively suppressed.

To investigate the improvement in the electrical performance by suppressing surface oxidation through interlayer insertion, top-gate TFTs shown in Fig. 2(a) were utilized. The fabrication process for the TFTs is illustrated in Fig. 2(b). After channel etching and source/drain patterning, an Al₂O₃ interlayer was inserted to protect the channel SnO. Devices with Al₂O₃ interlayers with thicknesses of 1.5 and 3 nm, as well as devices without interlayers, were fabricated simultaneously for electrical performance evaluation. These devices are denoted as IL-0 nm, IL-1.5 nm, and IL-3 nm, respectively. A 30 nm HfO₂ dielectric layer was then deposited on top of that stack, and the top gate was formed via a lift-off process. The HfO₂ layer functioned as a reliable gate dielectric without ferroelectric behavior (Fig. S1, ESI†).

Fig. 2 (a) Illustration of the fabricated top-gate SnO TFT. (b) Schematic of the fabrication process for the top-gate SnO TFT shown in (a).

Fig. 3(a)–(c) present the transfer characteristics of TFTs, i.e., the source–drain current (I_DS) as a function of the source–gate voltage (V_GS) for top-gate TFTs with different IL thicknesses (0, 1.5, and 3 nm). Notably, a hole accumulation layer forms at the surface in contact with the IL in this structure, which substantially impacts the device operation. The hysteresis behavior weakened as the IL thickness increased. Border traps commonly cause hysteresis;^20,28 therefore, the insertion of the IL is presumed to have effectively reduced the trapping and detrapping. Moreover, the field-effect mobility nearly doubled, increasing from 0.15 to 0.33 cm²/(Vs), while the on/off ratio was improved by approximately 2 to 4 times owing to the insertion of the IL. No significant change was observed in the SS. Table 1 and Fig. 3(d) and (e) summarize the key electrical parameters corresponding to the devices shown in Fig. 3(a)–(c). The output curves corresponding to each transfer curve are provided in Fig. S2 (ESI†). As shown in Fig. 3(e), a switching operation with negligible hysteresis was achieved for IL-3 nm. However, in the case of IL-1.5 nm, the direction of hysteresis reversed from counterclockwise to clockwise compared to that in IL-0 nm. A more detailed investigation was required to understand why the hysteresis decreased and even reversed the direction as the IL thickness increased. We hypothesized that factors other than the border trap density might contribute to this phenomenon.

Fig. 3 Transfer curves showing I_DS as a function of V_GS and corresponding μ_FE for (a) IL 0 nm, (b) IL 1.5 nm, and (c) IL 3nm. (d) Comparison of key electrical parameters for IL 0 nm, IL 1.5 nm, and IL 3 nm, including I_on/I_off, μ_FE, and SS. (e) Threshold voltage (V_th) extracted from the forward and reverse sweeps, illustrating the hysteresis direction and magnitude.

Table 1 Key electrical parameters as a function of interlayer (IL) thickness

	I on/Ioff	μ FE [cm^2 V^−1 s^−1]	S.S [V dec^−1]	V th,forward	V th,reverse
IL 0 nm	2.5 × 10^4	0.15	1.59	−0.45	−5.11
IL 1.5 nm	5.0 × 10^4	0.33	1.90	−3.39	−1.55
IL 3 nm	1.1 × 10^5	0.31	1.86	−2.59	−2.91

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To gain further insights, transfer curves were obtained by varying the gate bias sweep range. Fig. 4(a) shows the hysteresis behavior of IL-1.5 nm as a function of the V_GS sweep range. When the gate bias was swept in the sequence of 5 V → −5 V → 5 V, a counterclockwise hysteresis was observed, similar to that observed for IL-0 nm. The hysteresis voltage in the range of ±5 V for IL-1.5 nm was 0.87 V, significantly smaller than 2.61 V observed for IL-0 nm (Fig. S3, ESI†). This indicates a notable reduction in trapping and detrapping owing to the Al₂O₃ layer. For IL-0 nm, where a significant counterclockwise hysteresis was observed because of the relatively high border trap density, no reversal in hysteresis behavior was observed even with an increased gate bias sweep range of ±10 V; instead, the hysteresis window increased, attributed to enhanced trapping and detrapping within a higher bias range. However, when the gate bias sweep range was extended to ±10 V for IL-1.5 nm, the direction of the hysteresis reversed, which is noteworthy.

Fig. 4 (a) Transfer characteristics under different gate voltage sweep ranges for IL 1.5 nm. (b) Schematic of the border-trap-dominant case inducing a counterclockwise hysteresis. (c) Schematic of the oxygen-vacancy-migration-dominant case inducing a clockwise hysteresis.

Hysteresis in the direction opposite to that caused by border traps is predominantly attributed to the presence of mobile ions within the gate oxide.^20,33,34 In the case of p-type switching devices, this corresponds to clockwise hysteresis. Potential mobile ions driven by the gate bias in this system include alkali ions,³⁴ hydrogen ions,^35,36 and oxygen vacancies.^35,37,38 However, as the device fabrication was carried out in a class 1000 cleanroom without intentional ion doping, the migration of alkali ions can be ruled out. Therefore, the bias-induced migration of hydrogen ions or oxygen vacancies within the dielectric could be identified as a primary mechanism responsible for the hysteresis. Based on the TOF-SIMS data discussed below, however, the concentration of hydrogen impurities in the HfO₂ dielectric does not vary significantly with the presence or absence of the IL, and thus it is unlikely that hydrogen ions are responsible for the clockwise hysteresis. Consequently, the observed clockwise hysteresis can be attributed to the migration of ionized oxygen vacancies (V²⁺_O) induced by a relatively high gate bias. Ionized oxygen vacancy migration within HfO₂ under an electric field is a commonly observed phenomenon.^37–39 Additionally, when a gate bias of 10 V is applied, the resulting electric field is approximately 3 MV cm⁻¹, which is sufficient to induce oxygen vacancy migration.³⁷ In order to verify the presence of oxygen vacancies, Hf 4f and O 1s XPS spectra were analyzed (Fig. S4, ESI†). The Hf 4f_7/2 for HfO₂ appeared at 17.0 eV, and non-stoichiometric HfO_2−x exhibited a lower binding energy.^40,41 With IL insertion, the Hf 4f spectra shifted to lower energy, and deconvolution revealed a higher proportion of HfO_2−x in the HfO₂/Al₂O₃/SnO stack than in the HfO₂/SnO stack, suggesting oxygen vacancy formation. This observation is further supported by a slight increase in the oxygen-deficient component in the O 1s spectrum after IL insertion.

In summary, the relatively small electric field in the IL-1.5 nm device results in a counterclockwise hysteresis, primarily driven by trapping and detrapping (Fig. 4(b)). However, when the electric field increases to approximately 3 MV cm⁻¹, a clockwise hysteresis emerges because of the migration of ionized oxygen vacancies within the dielectric (Fig. 4(c)). The trapping and detrapping likely persisted under this condition, while the dominance of ionized oxygen vacancy migration appears to have overshadowed their effects. Oxygen vacancy migration might also occur in the IL-0 nm device. However, its effects are presumably masked by the abundance of border traps that exist at the HfO₂ interface. Furthermore, previous reports suggest that oxygen vacancies are more easily generated in an Al-doped HfO₂ than in a pristine HfO₂,^37,38,42 leading to enhanced formation of oxygen vacancies in the HfO₂/Al₂O₃ stack, which is consistent with our XPS results. By fabricating the IL-3 nm device with an increased IL thickness, we effectively reduced the voltage distributed across the HfO₂ layer. This reduction in the electric field suppressed oxygen vacancy migration, and enabled the device to operate with a negligible hysteresis. Furthermore, the 3 nm Al₂O₃ interlayer effectively suppressed the trapping and detrapping at the border trap sites of HfO₂, and thereby eliminated the counterclockwise hysteresis (Fig. 3(c)). In the bottom-gate configuration, all devices were driven through an identical SiO₂ gate dielectric as they were fabricated on the same SiO₂/Si substrate. Consequently, they exhibited similar hysteresis behavior (Fig. S5, ESI†), indicating that the dielectric material strongly influences the hysteresis characteristics.

In TFTs, organic impurities at the semiconductor/dielectric interface negatively impact the switching behavior.^4,19 To examine the effect of the Al₂O₃ interlayer on impurity levels, a SIMS analysis was conducted for IL-0 nm and IL-3 nm. Fig. 5(a) and (b) present the SIMS depth profiles of C⁻, CN⁻, H⁻, Si⁻, and Sn⁻ for IL-0 nm and IL-3 nm, respectively. The boundaries of the dielectric, semiconductor, and substrate layers could be inferred from the profiles of Sn⁻ and Si⁻. In the absence of an Al₂O₃ interlayer, organic impurities such as C⁻, CN⁻ from the HfO₂ ALD process accumulated significantly in the region where the hole accumulation layer forms (at the top of the SnO thin film). However, with the introduction of the interlayer, these organic impurities were effectively reduced. To enable semi-quantitative comparison, the impurity-to-Sn intensity ratios at the SnO/dielectric interface were calculated and are presented in Fig. S6 (ESI†). This suggests that the initial ligand exchange process during the ALD of HfO₂ occurred more efficiently on the Al₂O₃ surface than on the SnO surface. The observed retardation of ALD behavior on the layer-structured SnO surface, which has relatively few functional groups owing to its 2D-like nature, contrasts with that on the hydroxyl group-rich Al₂O₃ surface, aligning with expectations based on their surface structures.^17,19,43 As aforementioned, the concentration of hydrogen within HfO₂, which can act as mobile ions, was unaffected by the presence or absence of the IL.

Fig. 5 TOF-SIMS depth profiles showing the distributions of H⁻, C⁻, CN⁻, Si⁻, and Sn⁻ anions in (a) IL 0 nm and (b) IL 3 nm TFT devices.

Thus far, we primarily focused on the characteristics of the semiconducting channel layer and its interface between dielectric thin films. However, as the properties of the gate dielectric are also critical for transistor operation, we examined the dielectric properties as a function of Al₂O₃ IL thickness. Fig. 6(a) presents grazing-incidence X-ray diffraction (GIXRD) patterns of the HfO₂/SnO (IL-0 nm) and HfO₂/Al₂O₃/SnO (IL-1.5 nm, IL-3 nm) stacks. HfO₂ crystallized into the monoclinic phase during deposition on the SnO thin film (IL-0 nm), while it remained amorphous when an Al₂O₃ interlayer was present. This was evidenced by the detection of monoclinic (100), (200), and (120) planes exclusively in the IL-0 nm structure. A comprehensive investigation of the substrate-dependent variations in HfO₂ crystallinity is planned for our future studies. The dielectric constant of HfO₂, calculated by the capacitance density shown in Fig. S1 (ESI†), was confirmed to be 17.6, in line with reported values.^17,29,44,45 Such disparities in the crystallinity of the dielectric HfO₂ can result in variations in the gate leakage current in transistors. Fig. 6(b) illustrates the leakage current as a function of the electric field for the IL-0 nm, IL-1.5 nm, and IL-3 nm devices. The inset of Fig. 6(b) depicts the configuration of the metal–insulator–metal capacitor utilized for the leakage current measurements. In IL-0 nm, the leakage current was more than 10 times higher than those in IL-1.5 nm and IL-3 nm. This phenomenon is likely attributed to the presence of grain boundaries, which function as leakage current paths.⁴⁶ Furthermore, the insertion of the Al₂O₃ interlayer, which possesses a larger bandgap of 7 eV compared to 5 eV of HfO₂, also contributed to the effective reduction in gate leakage current. In addition, stable switching operation of the IL-3 nm device under ±1 MV cm⁻¹ bias stress was observed, as demonstrated in the ESI† (Fig. S7). This outcome supports the suppression of the gate leakage current and highlights the effectiveness of the Al₂O₃ interlayer in improving device reliability.

Fig. 6 (a) GIXRD patterns of the HfO₂/Al₂O₃/SnO stack as a function of the IL thickness. (b) Gate leakage current density as a function of the electric field for the HfO₂/Al₂O₃ stack. The inset illustrates the device stack structure.

To gain further insights into the microstructure of the SnO surface and dielectric crystallinity, high-resolution transmission electron microscopy (HRTEM) was performed on IL-0 nm and IL-3 nm stacks (Fig. 7(a) and (b)). Consistent with the XRD observations, the HfO₂ in IL-0 nm crystallized, whereas the HfO₂ in IL-3 nm remained amorphous (white-colored insets in Fig. 7(a) and (b)). However, as shown in (i) of Fig. 7(b), a partially crystallized monoclinic HfO₂ phase, not detected by XRD, was locally observed only near the interface. Within the bulk of the SnO thin film, well-aligned (001) planes were detected regardless of the presence or absence of the interlayer, consistent with reported results ((ii) of Fig. 7(a) and (b)).^14,17,19 Consistent with the observations in the XPS spectra in Fig. 1(b)–(d), the HRTEM analysis also revealed stark differences in surface phase purity depending on the presence of the interlayer. Local SnO₂ crystallites were identified on the surface of IL-0 nm ((iii) of Fig. 7(a)). In addition, an amorphized SnO owing to surface damage and oxidation via exposure to O₃ was observed. In contrast, in IL-3 nm, where the Al₂O₃ interlayer well protected the surface, the SnO₂ phase or amorphized SnO was not detected over the entire surface. Thus, the HRTEM microstructural analysis showed a high consistency with the XPS and XRD results, which further validates our findings.

Fig. 7 Cross-sectional HRTEM images of (a) IL 0 nm and (b) IL 3 nm, showing the stack structures. The inset shows a magnified view of the HfO₂ layer, along with its fast Fourier transform (FFT) pattern. The three FFT patterns at the bottom correspond to regions (i), (ii), and (iii) in the HRTEM images, revealing the crystallographic features of HfO₂, SnO, and SnO₂, respectively.

Conclusion

This study highlights the significant impact of insertion of an ultrathin Al₂O₃ interlayer between the metastable SnO channel and gate dielectric in the top-gate TFTs. In such devices, the fabrication process begins with the deposition of the semiconductor layer, followed by the synthesis of the dielectric layer on top. During this process, the semiconductor surface is inevitably exposed to the oxidants used in dielectric synthesis, resulting in performance degradation. Here, the interlayer could have a critical role in protecting the semiconductor channel surface, as evidenced by the substantial increase in field-effect mobility, improved on/off current ratio, and reduced hysteresis behavior. Through ARXPS, TOF-SIMS, XRD, and TEM, we elucidated key mechanisms driving these improvements: suppression of SnO oxidation and amorphization, reduction of organic impurities at the channel/dielectric interface, and elimination of hysteresis behavior through the suppression of border trap effects and oxygen vacancy migration. Furthermore, to the best of our knowledge, this study is the first on a top-gate TFT realized with a p-type channel deposited via ALD, which further emphasizes its importance in advancing the electronic device field. We believe that these findings pave the way for integration of p-type transistors into next-generation CMOS systems for monolithic 3D integrated circuits.

Author contributions

Minki Choe: conceptualization, thin-film characterization, device fabrication, investigation of electrical properties, and manuscript writing – draft. Seung Ho Ryu, Jihoon Jeon, Inhong Hwang, Jae Min Jeong, and Jae Yoon Shim: thin-film deposition and device fabrication. Noh-Hwal Park: device fabrication and bias stability measurements. Taek-Mo Chung: conceptualization and precursor synthesis. Seong Keun Kim: conceptualization, supervision, and writing – review. In-Hwan Baek: conceptualization, supervision, writing – review & editing, and funding acquisition. All authors participated in the general discussion.

Data availability

The data supporting this article have been included as a part of the ESI.†

Conflicts of interest

There are no conflicts to declare

Acknowledgements

This study was supported by the National Research Foundation of Korea (NRF) grant-funded by the Korean government (MSIT) (RS-2023-00279972) and Technology (KIAT) grant funded by the Korean government (MOTIE) (RS-2024-00409639, HRD Program for Industrial Innovation). This study was also supported by Korea Basic Science Institute (National Research Facilities and Equipment Center) grant (RS-2022-NF000904) and the Basic Science Research Program (RS-2022-NR070869) through the NRF, both funded by the Korean government (MOE).

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Footnote

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d5tc00399g

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