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Issue 10, 2014
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Packaging commercial CMOS chips for lab on a chip integration

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Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

Graphical abstract: Packaging commercial CMOS chips for lab on a chip integration

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Publication details

The article was received on 30 Jan 2014, accepted on 12 Mar 2014 and first published on 12 Mar 2014

Article type: Paper
DOI: 10.1039/C4LC00135D
Citation: Lab Chip, 2014,14, 1753-1766
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    Packaging commercial CMOS chips for lab on a chip integration

    T. Datta-Chaudhuri, P. Abshire and E. Smela, Lab Chip, 2014, 14, 1753
    DOI: 10.1039/C4LC00135D

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