Ultrathin annealing-free polymer layers: new opportunity to enhance mobility and stability of low-voltage thin-film organic transistors

Abstract

A critical challenge for organic electronics in current research is the dielectric layer and the corresponding interfacial engineering, which determine the mobility, the stability, the power consumption, the miniaturization and the flexibilization. In this work, we demonstrate an ultrathin annealing-free polymer layer (5 nm) with compact structure and perfect surface state, which shows the potential to address this challenge. The polymer displays an ultra-smooth surface and suitable surface energy (close to that of organic semiconductors), which facilitates the growth of semiconductors with large grain sizes and reduces the trap density, thus further enhancing the mobility and the stability of the devices. The compact structure and perfect surface state make the application of an ultra-thin device (55 nm dielectric layer and 10 nm semiconductor layer) and low-power consumption (10 V) possible. Furthermore, the annealing-free process indicates that the polymer can be fabricated on any substrates, and therefore flexible electronics can be expected. Such an efficient method with ultrathin dielectric and semiconductor layers provides us with a valuable approach to achieve miniaturized, low-power and low-cost device fabrication and can be extended to other nanodevices.

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Introduction

The investigation of the unprecedented development of organic field-effect transistors (OFETs)^1–8 shows that silicon dioxide (SiO₂) has played an indelible role working as a dielectric layer ever since the first OFETs were reported.⁹ The commercial availability of SiO₂/Si substrates was so convenient that they became the most popular platform for investigating the semiconductor materials in organic electronics.^10–15 Nevertheless, the utilization of SiO₂/Si substrates still suffers from three major challenges: (1) the defects on the top surface of SiO₂ are not well defined leading to interface trapping that may deteriorate the performance of the devices;^16–19 (2) to avoid predictable leakage current between the drain/source electrodes and the gate electrode, the thickness of SiO₂ was normally controlled to be no less than 300 nm,^10–15 resulting in a high operating voltage and high-power consumption of the device; (3) the rigid nature of the SiO₂ layer makes it impossible to be applied in flexible electronics, which is one of the most important advantages of organic electronics.

In order to overcome these problems, a thin organic (e.g. self-assembled monolayers (SAMs) or polymers) layer with compact structure and perfect surface state (smooth, defect-free and suitable surface energy) will be a good choice. However, the reported methods, such as the surface modification by using SAMs or alternative of polymer as the dielectric layer, can only solve one or two of the aforementioned problems. For example, the surface modification by self-assembled monolayers (SAMs) can ameliorate the surface of the SiO₂ and effectively improve the structural quality of the interface, and, thus the electronic properties of the interface.^20–27 However, the fabrication of SAMs is always complicated and time-consuming, and needs cautious and elaborate handling, which is unlikely to be helpful to decrease the leakage current when thinning the dielectric layer. On the other hand, the polymer dielectric layers can solve the first and third challenges; however, these polymer buffer layers usually require either a very thick layer (hundreds of nanometer) to reduce the leakage current or an annealing process to decrease the defects and form a compact structure^28–31 which, to a certain extent, increases the energy consumption and the cost of processing. Therefore, it is necessary to introduce a new buffer layer to avoid these processing steps.

Inspired by previously polymer buffer layers in the literature,^32,33 in this work, we introduce poly (pyromellitic dianhydride-co-4,4′-oxydianiline) (PPDO), the precursor of polyimide (PI) used in our previous work,^7,28 as the polymer buffer layer to modify the silicon dioxide (SiO₂). It is found that an ultrathin (5 nm) PPDO buffer layer without any further annealing treatment exhibits the best performance. We demonstrate this thin polymer layer (5 nm) with compact structure and perfect surface state, which shows potential to solve all the three challenges. This polymer displays an ultrasmooth surface (with the roughness of only 1.3 Å) and a suitable surface energy (close to organic semiconductors), which facilitates the growth of semiconductors with large grain sizes reducing the trap density, thus further enhancing the performance and the stability of the devices. The compact structure and perfect surface state make the application of ultra-thin device (55 nm dielectric layer and 10 nm semiconductor layer) and low-voltage supply (10 V) possible. Furthermore, the annealing-free process indicates that the polymer can be fabricated on any substrates, and therefore flexible electronics can be expected. Such efficient method with ultrathin dielectric and semiconductor layers provides us a valuable approach to achieve miniaturized, low-power and low-cost device fabrication and can be extended to other nanodevices.

Experimental section

Materials

Pentacene, PPDO (1.04 g ml⁻¹) and N,N-dimethylacetamide (DMAC) were purchased from Sigma-Aldrich. Pentacene was used as received without further purification. Silicon wafers with 50 nm thermally oxidized SiO₂ layer were purchased from Si-mat Company. PPDO (1 ml) was diluted with 10 ml DMAC into 0.09 g ml⁻¹ before use. Silicon wafers with 50 nm thermally oxidized SiO₂ layer used in the present study were directly used after plasma treatment under 300 W for 5 min.

Surface energy

The following equation^34–37 was to calculate the surface energy of different dielectrics. The dispersion (γ^d_s) and polar (γ^p_s) components of surface energy, and the total surface energy (γ_s) was obtained from the following equation.

The surface energy (γ_lv), the dispersion component (γ^d_lv), and the polar component (γ^p_lv) values used to solve this equation were, 72.2, 22.0, 50.2 mJ m⁻² for water, and 48.0, 29.0, 19.0 for ethylene glycol, respectively.

The unit-area capacitance of SiO₂ and PPDO/SiO₂ film: devices with sandwich structures were fabricated. The specific capacitance as a function of frequency was tested by Keithley 4200-SCS capacitance unit. The contact area was 0.08 cm². The capacitance of SiO₂ was 62 nF cm⁻² and PPDO/SiO₂ was 55 nF cm⁻² shown in Fig. S1.†

Devices fabrication

Bottom-gate top-contact OFETs were fabricated, pentacene films as the active layers. 10 nm-thick pentacene film was thermally evaporated at ultrahigh vacuum with a pressure 2 × 10⁻⁶ Pa with a rate of 0.05 Å s⁻¹, and then the 20 nm Au electrode deposited through a metal mask, and all the devices were tested by Keithley 4200-SCS semiconductor analyzer and a Micromanipulator 6150 probe station at ambient atmosphere. Atomic Force Microscopy (AFM) measurements were carried out on a Multimode Nanoscope IIIa instrument (Digital Instrument) in tapping mode with silicon cantilevers.

Results and discussion

The molecular structure of poly (pyromellitic dianhydride-co-4,4′-oxydianiline) (PPDO) is shown in Fig. 1a, and this polymer with mass concentration of 0.09 g ml⁻¹ in N,N-dimethylacetamide (DMAC) was spin coated (4000 rpm) (Fig. 1b) on the surface of silicon wafer with 50 nm thermal oxide layer (SiO₂) to form a 5 nm layer (Fig. S2†). This film was ultra-smooth with a root-mean-square (RMS) roughness (R_q) of only 1.3 Å analyzed by atomic force microscopy (AFM) (Fig. 1c). The corresponding height and length data of this film is shown in Fig. S3a,† which shows much smaller height variation than the surface of SiO₂ (R_q = 3.8 Å, Fig. 1d) with corresponding height and length data shown in Fig. S3b.† The depth map of one random small area on both surfaces (Fig. 1e and f) further confirms that the spin-coated PPDO film has a smoother surface and this kind of smooth surface has been proved that it can reduce physical traps and transport barriers on the surface.⁸ It is noted that there is annealing-free treatment to form this ultra-smooth layer after spin-coating, which is further confirmed by the UV-Vis absorption spectra shown in Fig. 1g. We attribute this phenomenon to the nanoscale (5 nm) buffer layer, in which the solvent is easier to volatilize from this system.

Fig. 1 (a) Chemical structure of PPDO. (b) Method to obtain this ultrathin polymer layer. AFM image of the morphology of (c) the ultrathin PPDO film on SiO₂ and (d) SiO₂. Depth map of the area on the surface of (e) PPDO (the area in the dotted line in (c)) and (f) SiO₂ (the area in the dotted line in (d)). (g) UV-Vis absorption spectra of PPDO without annealing and DMAC solvent.

It has been proved that a similar surface energy of the dielectric layer with the semiconductors is beneficial to the subsequent growth of the semiconductors, which facilitate the formation of large crystal grains of the semiconductors.^38–41 The surface energy of bare SiO₂ and PPDO/SiO₂ was evaluated by measuring the contact angles of two test liquids: water and ethylene glycol. The contact angles of water and ethylene glycol on both surfaces are shown in Fig. S4a–d,† respectively. The details to calculate the surface energy can be found in the Experimental section,^34–37 based on which the surface energy of PPDO/SiO₂ is calculated to be 42.68 mJ m⁻², which is, thus, much lower than that of the bare SiO₂ (81.35 mJ m⁻²). In addition, the surface energy of PPDO/SiO₂ (42.68 mJ m⁻²) was similar with pentacene (48.18 mJ m⁻²),³⁸ suggesting that the PPDO surface was in favour of the growth of pentacene with more ordered and large grain sizes.^39–41

To verify the interfacial effect of PPDO on the growth of the semiconductors afterwards, a 10 nm thick layer of pentacene was deposited on both bare SiO₂ and PPDO/SiO₂ surfaces. The morphological characteristics of the pentacene films on these two surfaces were investigated. The cross-sectional thickness is shown in Fig. S5.† It was clearly observed that a layer by layer growth mode took place on both surfaces. However, the grain size is obviously different. A larger grain size appeared on the surface of the PPDO/SiO₂ surface (∼3 μm) as compared to the bare SiO₂ surface (∼1 μm) (Fig. 2a and b). Moreover, the XRD pattern of the pentacene films on the PPDO/SiO₂ surface also showed a stronger intensity than that of the pentacene films on the bare SiO₂ surface, indicating a higher crystallinity of pentacene on the PPDO/SiO₂ surface (Fig. S6†). These results confirmed that our PPDO polymer films have a similar surface energy with the organic semiconductors and a very low surface roughness, which facilitates the formation of highly crystalline thin films with large crystal grains. It is worth noting that are no special conditions were adopted for the formation of the PPDO layer and no any further annealing process was applied. Therefore, such PPDO-polymer is a promising material for improved organic field-effect transistors.

Fig. 2 AFM image of the morphology of pentacene on (a) PPDO/SiO₂, and (b) SiO_2.

To assess the efficiency of this ultrathin PPDO layer, bottom-gate top-contact OFETs were fabricated. A vapor-deposition of a 20 nm Au layer served as source and drain electrodes with a patterned 10 nm thick layer of pentacene as the active layers. A schematic diagram of the cross-section of OFET is shown in Fig. 3a. Here, the devices with conventional SiO₂ insulator were used for comparison. Next, a multitude of devices with the same channel width (1000 μm) and different channel length were systematically examined. The mobility when using PPDO was superior to that without modification (Fig. 3b) based on the statistical data of 20 devices of each group investigated under otherwise the same conditions. As for the SiO₂ dielectric layer, it was found that the best mobility was about 0.09 cm² V⁻¹ s⁻¹ as calculated from the saturation region of the transfer curve and this performance was comparable with results in ref. 17. Excitingly, in our investigations the best mobility of the device based on PPDO/SiO₂ dielectric layer was up to 0.54 cm² V⁻¹ s⁻¹ indicating a six times higher performance. Other key parameters could also be extracted. The maximum current of the devices with a PPDO interfacial layer in a significant higher level (up to a factor of 38) than those without modification (Fig. 3c). Further, the threshold voltage of the devices with PPDO layer was lower than that with SiO₂ as insulators (Fig. 3d) with the I_on/I_off-ratio improving by an order of magnitude (Fig. 3e). Accordingly, the maximum interface trap density⁴² of a PPDO/SiO₂ surface (3.1 × 10¹² cm⁻² eV⁻¹) was less than that based on a pure SiO₂ surface (16.5 × 10¹² cm⁻² eV⁻¹). These results indicate that the functional melioration of the SiO₂ surface was well achieved by the PPDO. What's more, the performance evaluation of the device has greatly improved compared with previous pentacene-based transistors with the same model of dielectric layers shown in Table 1.^{32,33,43–47} Fig. 4 gives an example of the typical transfer (Fig. 4a and b) and output (Fig. 4c and d) electrical characteristics of the devices with and without PPDO under the same conditions. Both of these two kinds of devices showed the expected gate modulation of the drain current (I_D) in both the linear and saturation regimes. Simultaneously, the PPDO layer with 180 °C annealing treatment was also chosen for comparison due to the 165 °C boiling point of DMAC (solvent). However, this treatment decreased the performance (Fig. 5a), probably because the annealing process changed the microstructure of PPDO layer, which could be deduced from the red-shift of the UV-Vis absorption spectra (Fig. 5b) after annealing. The devices showed outstanding operating stabilities, even after 100 days (Fig. S7a and b†), and they were able to withstand more than 10³ on/off switch cycles of transfer characteristics. As is well known, the pentacene is sensitive to the water and oxygen in the air,⁴⁸ resulting in the decrease of performance, especially in the case of the ultrathin layers. As shown in Fig. 6a, a shelf-life test was carried out for over 100 days. The mobility of the devices based on SiO₂ dielectric layer decreased by 60% after 100 days. However, only 10% decrease of the performance was detected on the PPDO-based devices, probably due to atomic-scale roughness of the interface inducing more compact and high quality pentacene layers growing on this surface. We further investigated the contact resistance between the electrodes and semiconductor on the basis of previous literature reports.^49,50 The contact resistance of devices based on PPDO/SiO₂ dielectric layers (4 kΩ cm) was lower than that based on a SiO₂ insulator layers (550 kΩ cm) (Fig. 6b), which could be explained by the fact that the presence of PPDO facilitated the growth of pentacene into big grain size with fewer grain boundary, thus leading to fewer scattering events when charge injection occurs.

Fig. 3 (a) Schematic diagram of OFET, (b) distribution of the mobility based on 20 devices of each surface (PPDO/SiO₂ or SiO₂). (c) Maximum current of devices based on PPDO/SiO₂ insulator and SiO₂ insulator. (d) Threshold voltage of devices based on PPDO/SiO₂ insulator and SiO₂ insulator. (e) Ratio of I_on/I_off of devices based on PPDO/SiO₂ insulator and SiO₂ insulator.

Table 1 Summary of representative pentacene-based OFETs with (polymer + SiO₂) dielectric layers

Reference	Dielectric layer	Roughness (Å)	Thickness (nm)	μ (cm^2 v^−1 s^−1)	Operating voltage (V)	Annealing temperature (°C)
32	PS/SiO2	2	310	0.94	−100	120
33	PMMA/SiO2	N.A	108	0.21	−50	80
43	PS/SiO2	4.3	320	0.82	−40	110
	PS-brush/SiO2	4.4	320	0.82	−40	110
44	PS/SiO2	2.2	520	0.66	−100	80
40	PS1/SiO2	2	324	0.43	−100	80
	PS2/SiO2	2	331	0.43	−100	80
	PS3/SiO2	3	371	0.43	−100	80
	PS4/SiO2	3	450	0.4	−100	80
	PVA/SiO2	3	415	0.027	−100	80
	CPS/SiO2	9	313	0.22	−100	80
	PS-oxy/SiO2	3	324	0.24	−100	80
45	PMMA/SiO2	2.4	308	0.1	−50	120
	F4-TCNQ doped PMMA/SiO2	2.9	308	0.19	−50	120
Our results	PPDO/SiO2	1.3	55	0.54	−10	Annealing-free

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Fig. 4 Typical transfer characteristics (V_DS = −10 V) of the transistor based on (a) PPDO/SiO₂ insulator, and (b) SiO₂ insulator. Typical output characteristics of the transistor based on (c) PPDO/SiO₂ insulator, and (d) SiO₂ insulator.

Fig. 5 (a) Typical transfer characteristics (V_DS = −10 V) of the transistor. (b) UV-Vis absorption spectra of PPDO before and after annealing.

Fig. 6 (a) Percentage of mobility as a function of time (day), (b) plots of channel length versus resistance of devices, (black line: PPDO/SiO₂; red line: SiO₂).

Conclusions

In conclusion, an annealing-free ultrathin (5 nm) PPDO polymer was introduced into organic field-effect transistors. The results have shown that the PPDO polymer creates an ultra-smooth surface with similar surface energy of organic semiconductors, and which is beneficial for the growth of pentacene. The high quality of the polymer layer facilitate a lower trap density and lower contact resistance, leading to higher mobility and better stability compared with the devices without this polymer layer. The ultra-smooth surface makes it possible to achieve thin-film channel layer with high performance. Excitingly, the transistors with ultrathin (10 nm pentacene) channel layers show excellent performance with a hole mobility up to 0.54 cm² V⁻¹ s⁻¹, i.e. six-times higher than the device without this polymer layer. It is also worth noting that there no special conditions were adopted for the fabrication of the PPDO layer and no additional annealing process needed to be applied. These findings provide us a valuable approach to achieve miniaturized and low-cost device fabrication, and can be extended to other nanodevices. The further application of this polymer itself as an ultrathin dielectric layer in flexible OFETs is underway.

Acknowledgements

This work was funded by the Germany-China Joint Project TRR61 (DFGNSFC Transregio Project B3).

Notes and references

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Footnote

† Electronic supplementary information (ESI) available. See DOI: 10.1039/c6ra09750b

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