Area and Power Efficient Ternary Serial Adder Using Phase Composite ZnO Stack Channel FETs

Abstract

Multi-valued logic is the subject of ongoing investigation owing to its potential to reduce the complexity of logic circuits and interconnect lengths, thereby reduce system power consumption. In this work, ternary stack channel field-effect transistors (SCFETs) are used as a unit device to realize multi-valued logic. The thickness of each ZnO layer in an SCFET is modulated to obtain the device parameters to control the intermediate-state range and saturation current. Using the experimental results, the ternary circuits are modeled and simulated to demonstrate that the unique characteristics of SCFETs can be utilized in designing a ternary full adder. The designed ternary full adder requires only 12 devices (approximately 29% of the binary full adder device count). The ternary serial adder has a competitive power-delay product value of approximately 7 fJ at VDD = 1 V and an effective oxide thickness of 1 nm. These results indicate that SCFET-based ternary circuits are a promising alternative for extreme low-power applications.