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Issue 6, 2013
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Vertical nanowire array-based field effect transistors for ultimate scaling

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Nanowire-based field-effect transistors are among the most promising means of overcoming the limits of today's planar silicon electronic devices, in part because of their suitability for gate-all-around architectures, which provide perfect electrostatic control and facilitate further reductions in “ultimate” transistor size while maintaining low leakage currents. However, an architecture combining a scalable and reproducible structure with good electrical performance has yet to be demonstrated. Here, we report a high performance field-effect transistor implemented on massively parallel dense vertical nanowire arrays with silicided source/drain contacts and scaled metallic gate length fabricated using a simple process. The proposed architecture offers several advantages including better immunity to short channel effects, reduction of device-to-device variability, and nanometer gate length patterning without the need for high-resolution lithography. These benefits are important in the large-scale manufacture of low-power transistors and memory devices.

Graphical abstract: Vertical nanowire array-based field effect transistors for ultimate scaling

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The article was received on 20 Nov 2012, accepted on 21 Jan 2013 and first published on 23 Jan 2013

Article type: Paper
DOI: 10.1039/C3NR33738C
Citation: Nanoscale, 2013,5, 2437-2441
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    Vertical nanowire array-based field effect transistors for ultimate scaling

    G. Larrieu and X.-L. Han, Nanoscale, 2013, 5, 2437
    DOI: 10.1039/C3NR33738C

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