New strategies for catalyst nanoparticle placement in arbitrary patterns and non-planar geometries will likely accelerate the large scale device integration of epitaxial semiconductor nanowires (NWs) grown through the vapor-liquid-solid (VLS) process. Herein we report a technique for rational metal catalyst nanoparticle deposition based on galvanic displacement onto semiconductor surfaces through block copolymer micelle templates. Nanoparticle volumes and areal densities are controlled by the time in the plating solution and by mixing homopolymer with the micelle suspension, respectively. Above a minimal nanoparticle diameter, the mean diameters of epitaxial VLS-grown Si NWs scale directly with mean sizes of the template deposited nanoparticle seeds from which they are grown. The substrate selectivity and conformality of galvanic displacement makes possible two-level micro/nano-patterning in a variety of geometries by applying micellar templates over photolithographically patterned masks; the growth of single sub-50 nm diameter Si NWs in 600–700 nm diameter wells demonstrates a feature size reduction greater than one order of magnitude. Two-point electrical measurements across single NWs or a few NWs epitaxially bridging silicon-on-insulator electrodes after ex situ doping demonstrate the viability of this approach for epitaxial NW device integration.